Custom IC Design

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How to save subckt parameters in Spectre

Category: Custom IC Design

By Dessai

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updated over 5 years ago by Dessai

2 replies • 14510 views
Discussion

How to create an output expression for given expression using aged and fresh results

Category: Custom IC Design

By noramirkh

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updated over 5 years ago by noramirkh

4 replies • 14904 views
Discussion

Hierarchical member access in VerilogA

Category: Custom IC Design

By DimitarT

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updated over 5 years ago by Andrew Beckett

6 replies • 16646 views
Discussion

Accessing power dissipation in a Verilog module

Category: Custom IC Design

By vksinghal

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updated over 5 years ago by Andrew Beckett

1 replies • 13279 views
Discussion

Missing point in AMS simulation plot when the value of the consecutive points are same

Category: Custom IC Design

By RFStuff

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updated over 5 years ago by Andrew Beckett

1 replies • 13294 views
Discussion

Return a string from user-defined function in VerilogA

Category: Custom IC Design

By DimitarT

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updated over 5 years ago by Andrew Beckett

1 replies • 15828 views
Discussion

Monte Carlo Ocean XL: Interrupting simulations in a script

Category: Custom IC Design

By Martyniuk

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updated over 5 years ago by Andrew Beckett

1 replies • 13420 views
Discussion

technology file manager

Category: Custom IC Design

By skillEater

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updated over 5 years ago by Andrew Beckett

3 replies • 15101 views
Discussion

Parameters of a FINFET

Category: Custom IC Design

By ElectronLearn

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updated over 5 years ago by Andrew Beckett

3 replies • 17124 views
Discussion

extract min and max over corners for every variable step

Category: Custom IC Design

By skylink

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updated over 5 years ago by skylink

2 replies • 16360 views
Discussion

How to reduce parasitics from layout

Category: Custom IC Design

By jyoti kandpal

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updated over 5 years ago by FormerMember

1 replies • 15603 views
Discussion

Virtuosity: Looking Back at Virtuoso ADE Product Suite and Virtuoso Visualization and Analysis in 2019

Category: Custom IC Design

By Andrew Beckett

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started over 5 years ago

0 replies • 12837 views
Discussion

layout extraction avoid a specific area

Category: Custom IC Design

By S Liu

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updated over 5 years ago by Andrew Beckett

1 replies • 13240 views
Discussion

Programmatically set y-axis in VIVA in Log Scale

Category: Custom IC Design

By Paolo Minotti

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updated over 5 years ago by Andrew Beckett

6 replies • 18896 views
Discussion

How to flatten a hierarchical design?

Category: Custom IC Design

By Fari

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updated over 5 years ago by Andrew Beckett

1 replies • 15332 views

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