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Custom IC Design

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  • Discussion

    spicein different results

    Category: Custom IC Design

    By closyx

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    updated over 3 years ago by Andrew Beckett

    1 replies • 9709 views
  • Discussion

    Matlab interfacing with Virtuoso

    Category: Custom IC Design

    By sidm

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    updated over 3 years ago by Andrew Beckett

    11 replies • 15297 views
  • Discussion

    Loading simulation results into maestro explorer/assembler

    Category: Custom IC Design

    By Svilen64

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    updated over 3 years ago by Andrew Beckett

    3 replies • 4158 views
  • Discussion

    Quantizing sine wave

    Category: Custom IC Design

    By Farhan Ali 9216

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    •

    updated over 3 years ago by Andrew Beckett

    4 replies • 14363 views
  • Discussion

    Modifying/Editing Maestro/Assembler Test setup with text editor

    Category: Custom IC Design

    By greywanderer

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    updated over 3 years ago by greywanderer

    4 replies • 2781 views
  • Discussion

    supported psf format different between IC617 and IC618?

    Category: Custom IC Design

    By kkdesbois

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    updated over 3 years ago by kkdesbois

    2 replies • 10372 views
  • Discussion

    Why pin object is converted to shape in Abstract generator

    Category: Custom IC Design

    By knowledgeseeker

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    •

    updated over 3 years ago by Andrew Beckett

    1 replies • 9606 views
  • Discussion

    How to find "file signature" of design files in Cadence Virtuoso (schematics, layouts, symbols, etc.)

    Category: Custom IC Design

    By Cocacola

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    updated over 3 years ago by Andrew Beckett

    6 replies • 3103 views
  • Discussion

    Transient simulation termination by VerilogA model

    Category: Custom IC Design

    By Senan

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    updated over 3 years ago by Senan

    4 replies • 12108 views
  • Discussion

    Verilog Error

    Category: Custom IC Design

    By Lemi

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    updated over 3 years ago by Andrew Beckett

    1 replies • 12469 views
  • Discussion

    Layer Generation of Multiple Layers in Virtuoso

    Category: Custom IC Design

    By Tom Sawyer

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    •

    updated over 3 years ago by Andrew Beckett

    10 replies • 14297 views
  • Discussion

    clock buffer chain jitter measurement under deterministic supply noise

    Category: Custom IC Design

    By YutaoLiu

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    •

    updated over 3 years ago by FormerMember

    7 replies • 13465 views
  • Discussion

    Determine corner-dependent setting during operating point calculation with VerilogA model

    Category: Custom IC Design

    By FormerMember

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    •

    started over 3 years ago

    0 replies • 3607 views
  • Discussion

    Monte carlo simulation question

    Category: Custom IC Design

    By Holz

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    •

    updated over 3 years ago by Holz

    2 replies • 9606 views
  • Discussion

    how to plot THD against output voltage?

    Category: Custom IC Design

    By sahand1400

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    •

    updated over 3 years ago by FormerMember

    7 replies • 12990 views
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