Custom IC Design

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Discussion

Liberate (pass/file bisection)

Category: Custom IC Design

By kasula5

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started over 9 years ago

0 replies • 511 views
Discussion

Printed OFET PDK Development

Category: Custom IC Design

By ramkumarg

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updated over 9 years ago by robert11

2 replies • 13317 views
Discussion

Changing default settings of Virtuoso Layout XL

Category: Custom IC Design

By Clidre

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updated over 9 years ago by Clidre

2 replies • 18397 views
Discussion

How to fix layers after changing layer numbers in the technology file

Category: Custom IC Design

By Sheppy

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updated over 10 years ago by theopaone

5 replies • 18095 views
Discussion

how to attach a new device file in cadence virtuoso version 6.1.2

Category: Custom IC Design

By RAVI2100

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updated over 10 years ago by Quek

1 replies • 13689 views
Discussion

Making ruler value more visible

Category: Custom IC Design

By Identical

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updated over 10 years ago by Andrew Beckett

3 replies • 15164 views
Discussion

Parameterized Layout Design

Category: Custom IC Design

By skvishvakarma

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updated over 10 years ago by Sheppy

9 replies • 17176 views
Discussion

Import CDL, CDF paramter is not updated

Category: Custom IC Design

By tswong

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updated over 10 years ago by tswong

2 replies • 14941 views
Discussion

Virtuoso crashes when trying to instantiate a stacked VIA

Category: Custom IC Design

By Sheppy

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updated over 10 years ago by Sheppy

2 replies • 13976 views
Discussion

PSS+PNoise

Category: Custom IC Design

By analogy

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updated over 10 years ago by Andrew Beckett

3 replies • 950 views
Discussion

SPECTRE PNOISE and JITTER calculations

Category: Custom IC Design

By RRThomas

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updated over 10 years ago by RRThomas

6 replies • 19434 views
Discussion

Fingers and multiplier of MOSFET

Category: Custom IC Design

By jun1119

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updated over 10 years ago by Andrew Beckett

6 replies • 58540 views
Discussion

What controls "Value" vs Plotting on waveform window.

Category: Custom IC Design

By analogy

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updated over 10 years ago by Andrew Beckett

6 replies • 4855 views
Discussion

Cross function

Category: Custom IC Design

By analogy

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updated over 10 years ago by Andrew Beckett

1 replies • 17437 views
Discussion

verilogA model en operating point output

Category: Custom IC Design

By fabriceBG

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updated over 10 years ago by fabriceBG

2 replies • 13633 views

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