Custom IC Design

Latest Posts

Discussion

Schematic editor: how to change the color of the annotations?

Category: Custom IC Design

By dontpanic

$usertype
•
updated over 7 years ago by dontpanic

2 replies • 18173 views
Discussion

Plot Schematic Hierarchy into single file

Category: Custom IC Design

By HoWei

$usertype
•
updated over 7 years ago by HoWei

3 replies • 16956 views
Discussion

Monte Carlo simulation results have difference even in ideal circuits

Category: Custom IC Design

By sam jiang

$usertype
•
updated over 7 years ago by Andrew Beckett

1 replies • 14442 views
Discussion

How to add/configure new column in Monte Carlo result page (Summary & Yield), like Std Dev/mean

Category: Custom IC Design

By sjwprc

$usertype
•
updated over 7 years ago by Andrew Beckett

1 replies • 822 views
Discussion

How to write Monte Carlo file for FinFET?

Category: Custom IC Design

By Amin Zayed

$usertype
•
updated over 7 years ago by Andrew Beckett

1 replies • 14215 views
Discussion

Reversing the contents of an expanded bus in VIVA

Category: Custom IC Design

By CADcasualty

$usertype
•
updated over 7 years ago by Andrew Beckett

2 replies • 14859 views
Discussion

Documentation error for awvPlotWaveform function in Virtuoso Visualization and Analysis XL SKILL Reference manual

Category: Custom IC Design

By CADcasualty

$usertype
•
updated over 7 years ago by Andrew Beckett

2 replies • 14473 views
Discussion

Simulation and PEX

Category: Custom IC Design

By AllenD

$usertype
•
updated over 7 years ago by Andrew Beckett

1 replies • 16981 views
Discussion

RE: IBIS Version 6.1

Category: Custom IC Design

By kenambo

$usertype
•
started over 7 years ago

0 replies • 13676 views
Discussion

Skill command to delete label from layout

Category: Custom IC Design

By Ishant Anand

$usertype
•
updated over 7 years ago by Andrew Beckett

1 replies • 16923 views
Discussion

Creating a CNTFET model in cadence using veriloga

Category: Custom IC Design

By nikita6

$usertype
•
updated over 7 years ago by Shobhitkareer

1 replies • 16028 views
Discussion

Auto route STOP at symbol boundary?

Category: Custom IC Design

By goofycat

$usertype
•
updated over 7 years ago by Andrew Beckett

1 replies • 14234 views
Discussion

Extend schematic Check&Save for checking instance CDF parameter

Category: Custom IC Design

By HoWei

$usertype
•
updated over 7 years ago by Andrew Beckett

1 replies • 1214 views
Discussion

Monte Carlo mismatch on selected instances when these instances are defined by (nested) config files

Category: Custom IC Design

By HansB

$usertype
•
started over 7 years ago

0 replies • 14506 views
Discussion

Simulation is too slow

Category: Custom IC Design

By BaaB

$usertype
•
updated over 7 years ago by Saloni Chhabra

5 replies • 21837 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.