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Custom IC Design

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  • Discussion

    ELC : Simulation status : FAIL during db_spice

    Category: Custom IC Design

    By Hemal93

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    updated over 9 years ago by Hemal93

    6 replies • 14783 views
  • Discussion

    How to flatten layout cells and preserve pin names when pin names from different cells are the same

    Category: Custom IC Design

    By twen

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    •

    updated over 9 years ago by Andrew Beckett

    10 replies • 20047 views
  • Discussion

    Issues with pin connectivity in Layout

    Category: Custom IC Design

    By DavideP

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    updated over 9 years ago by DavideP

    2 replies • 25075 views
  • Discussion

    Error in Calibre LVS

    Category: Custom IC Design

    By srihari18

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    •

    updated over 9 years ago by Andrew Beckett

    1 replies • 16862 views
  • Discussion

    Run multiple ADE of the same schematic at the same time.

    Category: Custom IC Design

    By BaaB

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    •

    updated over 9 years ago by BaaB

    4 replies • 16707 views
  • Discussion

    ELC Error: Redefinition of the subckt

    Category: Custom IC Design

    By Hemal93

    $usertype

    •

    updated over 9 years ago by Hemal93

    2 replies • 14356 views
  • Discussion

    abstract generator: LEF does not contain ANTENNAGATEAREA

    Category: Custom IC Design

    By jsundermeyer

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    •

    updated over 9 years ago by jsundermeyer

    2 replies • 15492 views
  • Discussion

    BUG: Drawing path in Virtuoso 6.1.6 only possible in routing layers

    Category: Custom IC Design

    By Sheppy

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    •

    updated over 9 years ago by ColinSutlieff

    5 replies • 15438 views
  • Discussion

    Post Layout Simulation Error

    Category: Custom IC Design

    By sdineshkumar

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    •

    updated over 9 years ago by Andrew Beckett

    1 replies • 14137 views
  • Discussion

    How to save current through inherited connections in a cell with AMS

    Category: Custom IC Design

    By twen

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    •

    updated over 9 years ago by twen

    2 replies • 15074 views
  • Discussion

    How to create dependent voltage source?

    Category: Custom IC Design

    By BaaB

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    •

    updated over 9 years ago by Andrew Beckett

    9 replies • 23696 views
  • Discussion

    Assura LVS error

    Category: Custom IC Design

    By jdgriggs

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    •

    updated over 9 years ago by bartman

    6 replies • 17606 views
  • Discussion

    Error during the traversal of the config myLib myCell config

    Category: Custom IC Design

    By twen

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    •

    updated over 9 years ago by twen

    2 replies • 15203 views
  • Discussion

    Reproduce monte-carlo results with changed netlist

    Category: Custom IC Design

    By Daniel S

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    •

    updated over 9 years ago by Daniel S

    2 replies • 13951 views
  • Discussion

    Pin snapping in VirtuosoXL

    Category: Custom IC Design

    By climbnc

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    •

    updated over 9 years ago by ColinSutlieff

    1 replies • 14438 views
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