Custom IC Design

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Discussion

Recovering the deleted Symbol

Category: Custom IC Design

By SrujanPat2000

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updated over 3 years ago by SrujanPat2000

2 replies • 9439 views
Discussion

Changing the legend position in the Cadence results

Category: Custom IC Design

By Senan

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updated over 3 years ago by Senan

5 replies • 10978 views
Discussion

Files getting locked

Category: Custom IC Design

By RakeshPRG

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updated over 3 years ago by Andrew Beckett

1 replies • 13017 views
Discussion

DAC Verification (ENOB, SFDR, DNL, INL, THD measure)

Category: Custom IC Design

By Dali Lai

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updated over 3 years ago by Andrew Beckett

3 replies • 13380 views
Discussion

Error while simulating a project on ADE(XL)

Category: Custom IC Design

By FaisalShahzad

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updated over 3 years ago by XiongliangLai

6 replies • 14041 views
Discussion

Exporting statistical corner to different test of the same circuit

Category: Custom IC Design

By Senan

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updated over 3 years ago by Senan

2 replies • 9603 views
Discussion

Save Assembler output setup to csv with "Description" column?

Category: Custom IC Design

By StephanWeber

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updated over 3 years ago by StephanWeber

5 replies • 2301 views
Discussion

Remote-Host Simulation in ADE-L (or ADE Assembler) Does Not End

Category: Custom IC Design

By DrSeo

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updated over 3 years ago by DrSeo

1 replies • 9987 views
Discussion

How to run simulations in Explorer/Assembler starting from a netlist?

Category: Custom IC Design

By IceTea

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updated over 3 years ago by FormerMember

8 replies • 5195 views
Discussion

Inherited connections and VXL.....again.

Category: Custom IC Design

By kenc184

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updated over 3 years ago by kenc184

4 replies • 11294 views
Discussion

How do I set valid layers on bootup of Cadence Virtuoso XL?

Category: Custom IC Design

By dietSprunk

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updated over 3 years ago by Andrew Beckett

1 replies • 10149 views
Discussion

Any option in VLS to save one particular layer in hierarchy to a new view?

Category: Custom IC Design

By ssram

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updated over 3 years ago by Andrew Beckett

3 replies • 13745 views
Discussion

Accuracy of CROSS() function in Verilog-A

Category: Custom IC Design

By RFStuff

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updated over 3 years ago by atulkumar245

8 replies • 26634 views
Discussion

Creating a New PCELL from an existing Pcell and adding A new parameter to it

Category: Custom IC Design

By RFStuff

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updated over 3 years ago by Andrew Beckett

3 replies • 15448 views
Discussion

Creating a string expression in ADEL (or explorer) output section

Category: Custom IC Design

By Svilen64

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updated over 3 years ago by Svilen64

6 replies • 12509 views

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