Custom IC Design

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For a new machine, which RHEL?

Category: Custom IC Design

By kenc184

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updated 2 months ago by kenc184

3 replies • 1042 views
Discussion

Parameterization of transistor model BSIM4 parameters

Category: Custom IC Design

By Sourav Chakraborty

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started 2 months ago

0 replies • 647 views
Discussion

Verilog A: Generate different $random values for each Monte Carlo iteration

Category: Custom IC Design

By MC20250412421

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updated 2 months ago by MC20250412421

6 replies • 1500 views
Discussion

Convert Cadence Spectre to Cadence Orcad

Category: Custom IC Design

By SC202412036016

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started 2 months ago

0 replies • 792 views
Discussion

Voltus-Fi-XL : generated path of mergedCurrents.rpt

Category: Custom IC Design

By SY202508201356

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started 2 months ago

0 replies • 771 views
Discussion

setting environment variables from schematic?

Category: Custom IC Design

By unSkilled

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started 2 months ago

0 replies • 729 views
Discussion

STB Analysis Breakpoint Selection and Nyquist Plot Support in Cadence

Category: Custom IC Design

By Eleanor Grace

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updated 2 months ago by JankoK

3 replies • 1228 views
Discussion

stb results different when iprobe placed at different location of the loop

Category: Custom IC Design

By a048

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updated 2 months ago by Frank Wiedmann

3 replies • 1230 views
Discussion

giolib045 "archaeology" (origin of giolib045.lib, giolib045.gds files)

Category: Custom IC Design

By GS202507021424

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started 2 months ago

0 replies • 325 views
Discussion

Schematic editor 2D array signal

Category: Custom IC Design

By kramnik

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updated 2 months ago by Andrew Beckett

1 replies • 886 views
Discussion

automate creration of calibre view from extraction for multiple extracted corners

Category: Custom IC Design

By micipici

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updated 2 months ago by Andrew Beckett

1 replies • 988 views
Discussion

Automatic routing using Cadence Virtuoso IC6.18.120

Category: Custom IC Design

By hoangtn3702

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started 2 months ago

0 replies • 836 views
Discussion

How to greate guard ring for Cadence GPDK FinFet?

Category: Custom IC Design

By hesaliveJim

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updated 2 months ago by hesaliveJim

2 replies • 1096 views
Discussion

ADE ViVA Plotting Template: Where is it stored and how to edit?

Category: Custom IC Design

By StephanWeber

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updated 2 months ago by StephanWeber

2 replies • 1072 views
Discussion

How to load viaGetViaOptions Function inside PCELL

Category: Custom IC Design

By Esteban Saavedra

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updated 2 months ago by Andrew Beckett

4 replies • 1144 views

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