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Custom IC Design

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  • Discussion

    "None of the properties 'lastSchematicExtraction' or 'syLastExtraction' was found" problem

    Category: Custom IC Design

    By archive archive

    •

    updated over 15 years ago by Andrew Beckett

    6 replies • 9043 views
  • Discussion

    problems with calibre lvs

    Category: Custom IC Design

    By Francy Francy

    •

    updated over 15 years ago by tkhan

    1 replies • 17292 views
  • Discussion

    ADE L | post-layout simulation | input.scs error

    Category: Custom IC Design

    By Rbaca Rbaca

    •

    updated over 15 years ago by Quek

    4 replies • 13974 views
  • Discussion

    ADE-L asking for license when using "schematic menus"

    Category: Custom IC Design

    By tkhan tkhan

    •

    updated over 15 years ago by tkhan

    7 replies • 2411 views
  • Discussion

    ultrasim partitioning error, can I decalre bias node as voltage regulator output?

    Category: Custom IC Design

    By huber huber

    •

    updated over 15 years ago by Andre Baguenie

    2 replies • 13500 views
  • Discussion

    autosave option in 6.1.3 version

    Category: Custom IC Design

    By shushan shushan

    •

    updated over 15 years ago by chlascrew

    7 replies • 15817 views
  • Discussion

    spectre RF pss sweep error

    Category: Custom IC Design

    By kivvzhou kivvzhou

    •

    updated over 15 years ago by Andrew Beckett

    4 replies • 14787 views
  • Discussion

    ASSURA LVS errors

    Category: Custom IC Design

    By Dennis Faber Dennis Faber

    •

    updated over 15 years ago by Quek

    3 replies • 14556 views
  • Discussion

    Operating region

    Category: Custom IC Design

    By jugemu1234 jugemu1234

    •

    updated over 15 years ago by Dennis Faber

    4 replies • 73600 views
  • Discussion

    extract specified layout net 5141 (Assura & pvs)

    Category: Custom IC Design

    By stuso stuso

    •

    updated over 15 years ago by Andrew Beckett

    3 replies • 1642 views
  • Discussion

    Ultrasim partitioning guidelines

    Category: Custom IC Design

    By paulaos paulaos

    •

    started over 15 years ago

    0 replies • 12797 views
  • Discussion

    Plotting pole/zero results

    Category: Custom IC Design

    By Grover Grover

    •

    updated over 15 years ago by Andrew Beckett

    7 replies • 8428 views
  • Discussion

    Set Context / Calibre RVE?

    Category: Custom IC Design

    By PolygonSlinger PolygonSlinger

    •

    updated over 15 years ago by kbhow

    2 replies • 16091 views
  • Discussion

    comparission of two GDS

    Category: Custom IC Design

    By sailesh sailesh

    •

    updated over 15 years ago by stuso

    5 replies • 18304 views
  • Discussion

    Like to extract Some layout nets new layout (new Cell)

    Category: Custom IC Design

    By Satya Satya

    •

    updated over 15 years ago by Quek

    6 replies • 14927 views
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