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Custom IC Design

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  • Discussion

    How to stop Ocean script from UINX

    Category: Custom IC Design

    By mgkang

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    updated over 3 years ago by mgkang

    2 replies • 9697 views
  • Discussion

    schematic vs symbol pinorder.

    Category: Custom IC Design

    By kenc184

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    updated over 3 years ago by kenc184

    5 replies • 13353 views
  • Discussion

    Can't get results from a PAC sim

    Category: Custom IC Design

    By forXTer

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    updated over 3 years ago by Andrew Beckett

    5 replies • 3164 views
  • Discussion

    How to obtain Discrete-Time (DT) response from a switched-cap (SC) circuit (integrator)?

    Category: Custom IC Design

    By bernd2700

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    updated over 3 years ago by Frank Wiedmann

    52 replies • 36880 views
  • Discussion

    Plot all digital traces in one subwindow

    Category: Custom IC Design

    By LuighiV

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    updated over 3 years ago by Andrew Beckett

    6 replies • 12632 views
  • Discussion

    Assembler: possible to re-evaluate only results yielding "eval err" right after simulation?

    Category: Custom IC Design

    By dontpanic

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    updated over 3 years ago by dontpanic

    2 replies • 3914 views
  • Discussion

    Maestro Expression Migration Problem

    Category: Custom IC Design

    By Kevin Buck

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    updated over 3 years ago by Kevin Buck

    3 replies • 10484 views
  • Discussion

    how to update "design" when copy testbench

    Category: Custom IC Design

    By sjwprcker

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    updated over 3 years ago by Andrew Beckett

    1 replies • 1712 views
  • Discussion

    Documentation about VNL netlist format

    Category: Custom IC Design

    By marcelpreda

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    updated over 3 years ago by marcelpreda

    2 replies • 9100 views
  • Discussion

    Writing into a file in Verilog-A Model

    Category: Custom IC Design

    By Ketrin

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    updated over 3 years ago by Ketrin

    2 replies • 9857 views
  • Discussion

    Sweep the real inductor value in virtuoso

    Category: Custom IC Design

    By Detailer

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    updated over 3 years ago by Andrew Beckett

    4 replies • 12982 views
  • Discussion

    Could I run only one "runPlan" in Verifier?

    Category: Custom IC Design

    By SpiceMonkey

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    updated over 3 years ago by Andrew Beckett

    3 replies • 1934 views
  • Discussion

    Pnoise analysis of a clock divider with uneven even/odd output cycles

    Category: Custom IC Design

    By csn165309964

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    updated over 3 years ago by FormerMember

    5 replies • 4703 views
  • Discussion

    Changing Schematic Property Value in CIW Window

    Category: Custom IC Design

    By bjlanza

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    updated over 3 years ago by bjlanza

    2 replies • 9271 views
  • Discussion

    How to change VIVA zoom time-axis (Shift+ mouse scroll)

    Category: Custom IC Design

    By Nader Fathy

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    •

    updated over 3 years ago by Andrew Beckett

    5 replies • 12281 views
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