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Custom IC Design

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  • Discussion

    Layout Cannot Show PDK Instance Graph

    Category: Custom IC Design

    By ovicovic

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    updated over 3 years ago by Andrew Beckett

    1 replies • 11057 views
  • Discussion

    About finding the cellname of .oa files

    Category: Custom IC Design

    By lingtao jiang

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    •

    updated over 3 years ago by Andrew Beckett

    1 replies • 8922 views
  • Discussion

    Re: command line to select psf directory to allow DC annotation on schematic

    Category: Custom IC Design

    By slim15

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    •

    updated over 3 years ago by Andrew Beckett

    1 replies • 9269 views
  • Discussion

    Installscape stops downloading

    Category: Custom IC Design

    By a2tech

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    •

    updated over 3 years ago by Andrew Beckett

    1 replies • 8808 views
  • Discussion

    VerilogA SR Latch with digital output

    Category: Custom IC Design

    By delgsy

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    •

    started over 3 years ago

    0 replies • 10928 views
  • Discussion

    name of nets inside deepprobe

    Category: Custom IC Design

    By Svilen64

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    •

    updated over 3 years ago by Svilen64

    2 replies • 11568 views
  • Discussion

    how to section comment in a DSPF file

    Category: Custom IC Design

    By Svilen64

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    •

    updated over 3 years ago by Svilen64

    2 replies • 12231 views
  • Discussion

    How to stop Ocean script from UINX

    Category: Custom IC Design

    By mgkang

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    •

    updated over 3 years ago by mgkang

    2 replies • 9607 views
  • Discussion

    schematic vs symbol pinorder.

    Category: Custom IC Design

    By kenc184

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    •

    updated over 3 years ago by kenc184

    5 replies • 13213 views
  • Discussion

    Can't get results from a PAC sim

    Category: Custom IC Design

    By forXTer

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    •

    updated over 3 years ago by Andrew Beckett

    5 replies • 3121 views
  • Discussion

    How to obtain Discrete-Time (DT) response from a switched-cap (SC) circuit (integrator)?

    Category: Custom IC Design

    By bernd2700

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    •

    updated over 3 years ago by Frank Wiedmann

    52 replies • 36298 views
  • Discussion

    Plot all digital traces in one subwindow

    Category: Custom IC Design

    By LuighiV

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    •

    updated over 3 years ago by Andrew Beckett

    6 replies • 12483 views
  • Discussion

    Assembler: possible to re-evaluate only results yielding "eval err" right after simulation?

    Category: Custom IC Design

    By dontpanic

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    •

    updated over 3 years ago by dontpanic

    2 replies • 3887 views
  • Discussion

    Maestro Expression Migration Problem

    Category: Custom IC Design

    By Kevin Buck

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    •

    updated over 3 years ago by Kevin Buck

    3 replies • 10371 views
  • Discussion

    how to update "design" when copy testbench

    Category: Custom IC Design

    By sjwprcker

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    •

    updated over 3 years ago by Andrew Beckett

    1 replies • 1692 views
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