Custom IC Design

Latest Posts

Discussion

All pins on schematics unconnected to their attached wires when importing EDIF from Siemens,

Category: Custom IC Design

By DavidGogiber
•
updated 6 days ago by Andrew Beckett

4 replies • 577 views
Discussion

Cannot Copy Variable to Other Tests

Category: Custom IC Design

By MM202507017815
•
updated 8 days ago by Andrew Beckett

1 replies • 223 views
Discussion

Cadence PEX Directory Creation - Unable to Create the Directory for Netlist

Category: Custom IC Design

By ranaya
•
updated 11 days ago by ranaya

2 replies • 306 views
Discussion

Cadence Parasitic Extraction - Location / Directory Issue

Category: Custom IC Design

By ranaya
•
updated 11 days ago by Andrew Beckett

1 replies • 225 views
Discussion

Automating Library Reference Change with Additional Parameters in New Library

Category: Custom IC Design

By AN202507174258
•
started 13 days ago

0 replies • 228 views
Discussion

For a new machine, which RHEL?

Category: Custom IC Design

By kenc184
•
updated 14 days ago by kenc184

3 replies • 493 views
Discussion

Parameterization of transistor model BSIM4 parameters

Category: Custom IC Design

By Sourav Chakraborty
•
started 14 days ago

0 replies • 256 views
Discussion

Verilog A: Generate different $random values for each Monte Carlo iteration

Category: Custom IC Design

By MC20250412421
•
updated 16 days ago by MC20250412421

6 replies • 831 views
Discussion

Convert Cadence Spectre to Cadence Orcad

Category: Custom IC Design

By SC202412036016
•
started 16 days ago

0 replies • 388 views
Discussion

Voltus-Fi-XL : generated path of mergedCurrents.rpt

Category: Custom IC Design

By SY202508201356
•
started 16 days ago

0 replies • 396 views
Discussion

setting environment variables from schematic?

Category: Custom IC Design

By unSkilled
•
started 17 days ago

0 replies • 326 views
Discussion

STB Analysis Breakpoint Selection and Nyquist Plot Support in Cadence

Category: Custom IC Design

By Eleanor Grace
•
updated 18 days ago by JankoK

3 replies • 605 views
Discussion

quantus parasitic extraction vs. SKY130 PDK

Category: Custom IC Design

By GS202507021424
•
started 25 days ago

0 replies • 433 views
Discussion

stb results different when iprobe placed at different location of the loop

Category: Custom IC Design

By a048
•
updated 25 days ago by Frank Wiedmann

3 replies • 672 views
Discussion

giolib045 "archaeology" (origin of giolib045.lib, giolib045.gds files)

Category: Custom IC Design

By GS202507021424
•
started 27 days ago

0 replies • 256 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.