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Custom IC Design

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  • Discussion

    spectre.out file in psf directory

    Category: Custom IC Design

    By nicola91it

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    updated over 6 years ago by Andrew Beckett

    3 replies • 17569 views
  • Discussion

    Verilog-A Oscillator Phase noise

    Category: Custom IC Design

    By sherifali

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    started over 6 years ago

    0 replies • 13819 views
  • Discussion

    Issue with multiple QRC runs

    Category: Custom IC Design

    By Suryansh Singh

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    •

    updated over 6 years ago by Suryansh Singh

    2 replies • 13581 views
  • Discussion

    Virtuoso crashing

    Category: Custom IC Design

    By sray

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    •

    updated over 6 years ago by Andrew Beckett

    1 replies • 14310 views
  • Discussion

    Accuracy of Glitches Observed in Transient Simulation

    Category: Custom IC Design

    By anurans

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    •

    updated over 6 years ago by Andrew Beckett

    1 replies • 13774 views
  • Discussion

    maximum run numbers for MC sim

    Category: Custom IC Design

    By sjwprc

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    •

    updated over 6 years ago by sjwprc

    2 replies • 13721 views
  • Discussion

    how to setup and run multiple STB simulation in a single state

    Category: Custom IC Design

    By Pic Hao

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    updated over 6 years ago by sjwprc

    2 replies • 18287 views
  • Discussion

    寄生参数提取之后进行spectre仿真出错

    Category: Custom IC Design

    By langj17

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    updated over 6 years ago by sjwprc

    1 replies • 14495 views
  • Discussion

    square pin in schematic

    Category: Custom IC Design

    By zssfred

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    updated over 6 years ago by zssfred

    2 replies • 14174 views
  • Discussion

    [Virtuoso]Can I get SPICE model parameters of MOSFETs in library?

    Category: Custom IC Design

    By Leey

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    updated over 6 years ago by Frank Wiedmann

    2 replies • 8121 views
  • Discussion

    Pegasus LVS GUI to Load last selected Rule Set

    Category: Custom IC Design

    By hchan

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    •

    started over 6 years ago

    0 replies • 13237 views
  • Discussion

    VSR multi-level auto routing

    Category: Custom IC Design

    By henriqueiesam

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    started over 6 years ago

    0 replies • 13219 views
  • Discussion

    Timestamp warning when using ADE Assembler (Maestro)

    Category: Custom IC Design

    By HoWei

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    •

    started over 6 years ago

    0 replies • 13073 views
  • Discussion

    How to check simulation time of block ?

    Category: Custom IC Design

    By Asako

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    started over 6 years ago

    0 replies • 13078 views
  • Discussion

    define specs in adexl in text editor or batch mode? or batch tool for checking vdsat and vsat_margin?

    Category: Custom IC Design

    By monglebest

    $usertype

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    updated over 6 years ago by monglebest

    2 replies • 13824 views
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