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Custom IC Design

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  • Discussion

    List of latches used in netlist ?

    Category: Custom IC Design

    By roopakvasa

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    updated over 8 years ago by Quek

    1 replies • 13165 views
  • Discussion

    Calibre LVS with simulated sonnet component

    Category: Custom IC Design

    By Juanelin

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    updated over 8 years ago by Quek

    1 replies • 14440 views
  • Discussion

    changing via using skill

    Category: Custom IC Design

    By GirishBS181

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    •

    updated over 8 years ago by GirishBS181

    2 replies • 14116 views
  • Discussion

    Path drawn in Cadence Vituoso Layout Editor seems to get attached with adjacent Via

    Category: Custom IC Design

    By jdp721

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    updated over 8 years ago by jdp721

    2 replies • 15390 views
  • Discussion

    why is the input referred noise not proportional to the output noise?

    Category: Custom IC Design

    By MarcoL

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    updated over 8 years ago by MarcoL

    5 replies • 4078 views
  • Discussion

    Running an external shell script from within a Verilog-a block

    Category: Custom IC Design

    By mwb1

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    updated over 8 years ago by chanakaya

    1 replies • 13637 views
  • Discussion

    ICS6.1.7-64b.78 gravity and cross cursor

    Category: Custom IC Design

    By RVERP

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    updated over 8 years ago by RVERP

    6 replies • 15077 views
  • Discussion

    Error message: port cannot be drained

    Category: Custom IC Design

    By PatrikOsgnach

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    updated over 8 years ago by PatrikOsgnach

    1 replies • 14065 views
  • Discussion

    Selection of non-visible object

    Category: Custom IC Design

    By robdohanyos

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    updated over 8 years ago by Andrew Beckett

    1 replies • 14469 views
  • Discussion

    How to add Pwr sensitivity to a bus

    Category: Custom IC Design

    By mbugbee

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    •

    updated over 8 years ago by Andrew Beckett

    2 replies • 13604 views
  • Discussion

    Search Form creation What field should be used ?

    Category: Custom IC Design

    By JackPro

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    updated over 8 years ago by Andrew Beckett

    1 replies • 13095 views
  • Discussion

    determine the simulation time of compact model in verilog-A

    Category: Custom IC Design

    By samer1

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    updated over 8 years ago by samer1

    3 replies • 14201 views
  • Discussion

    VPRBS Source

    Category: Custom IC Design

    By BrJaWr

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    •

    updated over 8 years ago by chanakaya

    1 replies • 20439 views
  • Discussion

    PWM-ASK modulated input to Envelop Detector

    Category: Custom IC Design

    By bharshitha

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    •

    updated over 8 years ago by bharshitha

    2 replies • 14342 views
  • Discussion

    DRD halo shape

    Category: Custom IC Design

    By Eduardas

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    •

    updated over 8 years ago by Andrew Beckett

    1 replies • 13144 views
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