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Custom IC Design

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  • Discussion

    Execution of ocean script in Cadence IC 6.1.5 and Cadence IC 5.1.41

    Category: Custom IC Design

    By Lings

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    updated over 11 years ago by Andrew Beckett

    5 replies • 14544 views
  • Discussion

    Layout GXL: Flight wires not displaying

    Category: Custom IC Design

    By wewa

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    updated over 11 years ago by wewa

    4 replies • 15975 views
  • Discussion

    How to execute a c programme in UNIX using SKILL

    Category: Custom IC Design

    By AmitBiswas

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    updated over 11 years ago by Andrew Beckett

    1 replies • 13285 views
  • Discussion

    VerilogA models in Cadence

    Category: Custom IC Design

    By Sali

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    updated over 11 years ago by Sali

    12 replies • 21537 views
  • Discussion

    LVS does not accept proper termOrder

    Category: Custom IC Design

    By Kabal

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    updated over 11 years ago by Kabal

    9 replies • 19370 views
  • Discussion

    Adding Layout block from Encounter to custom design

    Category: Custom IC Design

    By Kabal

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    updated over 11 years ago by Andrew Beckett

    6 replies • 16265 views
  • Discussion

    How-to edit CGSO and CGDO parameters and resimulate

    Category: Custom IC Design

    By cozdag

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    updated over 11 years ago by Andrew Beckett

    1 replies • 14846 views
  • Discussion

    Parasitic extraction of standalone metal traces (IC6.1.5)

    Category: Custom IC Design

    By Wes8

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    updated over 11 years ago by Andrew Beckett

    1 replies • 14717 views
  • Discussion

    How to add noise in v source?

    Category: Custom IC Design

    By madhusudha

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    updated over 11 years ago by Andrew Beckett

    3 replies • 28409 views
  • Discussion

    Transient Noise Analysis | Noise File

    Category: Custom IC Design

    By pitter

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    updated over 11 years ago by Andrew Beckett

    3 replies • 17936 views
  • Discussion

    Hierarchy Editor - Setting schematic view recursively within a tree

    Category: Custom IC Design

    By cdonovan

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    updated over 11 years ago by cdonovan

    2 replies • 2375 views
  • Discussion

    DRC error in resistor layout

    Category: Custom IC Design

    By whitefan

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    updated over 11 years ago by whitefan

    1 replies • 14635 views
  • Discussion

    Getting back source layout from gds

    Category: Custom IC Design

    By ImonMondal

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    updated over 11 years ago by ImonMondal

    2 replies • 13867 views
  • Discussion

    simulating for sigma delta noise folding due to charge pump nonlinearity

    Category: Custom IC Design

    By vamshiky

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    updated over 11 years ago by Andrew Beckett

    5 replies • 15888 views
  • Discussion

    Modify netlist of a block and resimulate (CDL.... CDF....)

    Category: Custom IC Design

    By cozdag

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    updated over 11 years ago by Andrew Beckett

    1 replies • 17521 views
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