Custom IC Design

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Discussion

Virtuoso recovery from license server interruption?

Category: Custom IC Design

By drdanmc

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updated over 3 years ago by Andrew Beckett

1 replies • 10730 views
Discussion

Using Virtuoso without ADE explorer

Category: Custom IC Design

By micipici

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updated over 3 years ago by micipici

2 replies • 9918 views
Discussion

Function to skip start of a signal

Category: Custom IC Design

By SteveVrk

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updated over 3 years ago by Andrew Beckett

4 replies • 11290 views
Discussion

cannot specify instances during Monte Carlo setup

Category: Custom IC Design

By delgsy

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updated over 3 years ago by Andrew Beckett

8 replies • 12624 views
Discussion

Option nullmfactorcorrelation for MonteCarlo mismatch simulation

Category: Custom IC Design

By acharlet

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started over 3 years ago

0 replies • 9525 views
Discussion

Term Order setup for spice reference files

Category: Custom IC Design

By AncisMichele

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updated over 3 years ago by AncisMichele

2 replies • 11127 views
Discussion

Two step trimming in Maestro Assembler. Difficulty encountered trying to calculate the trimming code in the second trimming step.

Category: Custom IC Design

By IceTea

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updated over 3 years ago by IceTea

5 replies • 12079 views
Discussion

VerilogA $fopen issues when used in a loop

Category: Custom IC Design

By AAbdelRahman

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updated over 3 years ago by AAbdelRahman

6 replies • 13420 views
Discussion

Saving Assistants' location in Schematic Editor

Category: Custom IC Design

By AncisMichele

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updated over 3 years ago by AncisMichele

2 replies • 1304 views
Discussion

Seal-Ring DRC errors

Category: Custom IC Design

By Senan

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started over 3 years ago

0 replies • 10898 views
Discussion

Locating a result value from montecarlo run table in Cadence Virtuoso

Category: Custom IC Design

By Senan

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updated over 3 years ago by Senan

2 replies • 10145 views
Discussion

Dynamic paramters "temp" doesn't work? (Solver = Ultrasim, transient analysis)

Category: Custom IC Design

By SpiceMonkey

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updated over 3 years ago by Andrew Beckett

3 replies • 2494 views
Discussion

analog digital output average mean value

Category: Custom IC Design

By abdurrahman0234

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updated over 3 years ago by FormerMember

21 replies • 19694 views
Discussion

VerilogA loop generate constructs not defining multiple sub modules

Category: Custom IC Design

By AAbdelRahman

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updated over 3 years ago by AAbdelRahman

8 replies • 14121 views
Discussion

How to measure node to node capacitance?

Category: Custom IC Design

By Holz

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updated over 3 years ago by FormerMember

3 replies • 13655 views

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