Custom IC Design

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Discussion

Verilog-A Parser shows an error but simulation runs successfully with 0 errors

Category: Custom IC Design

By ElZorro

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updated over 3 years ago by ElZorro

2 replies • 12765 views
Discussion

Conditional netlisting of instance depending on CDF parameter value

Category: Custom IC Design

By JackCadnece

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updated over 3 years ago by JackCadnece

2 replies • 10258 views
Discussion

Liberate - Constraint search failed

Category: Custom IC Design

By iamKarthikBK

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updated over 3 years ago by iamKarthikBK

4 replies • 2563 views
Discussion

How to query the Assembler results database for an evaluated expression?

Category: Custom IC Design

By Brad RFeng

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updated over 3 years ago by Andrew Beckett

5 replies • 11677 views
Discussion

user defined parameter in dynamic parameter transient simulation

Category: Custom IC Design

By GirishW

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updated over 3 years ago by GirishW

2 replies • 13136 views
Discussion

Moving average offset in verilogA

Category: Custom IC Design

By jorgevdelacruzN

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updated over 3 years ago by slim15

2 replies • 14140 views
Discussion

Layout Instantiation shows a line

Category: Custom IC Design

By amssshubham

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updated over 3 years ago by Andrew Beckett

1 replies • 9249 views
Discussion

print montecarlo correlation table

Category: Custom IC Design

By Michael Figueiredo

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updated over 3 years ago by Andrew Beckett

1 replies • 9906 views
Discussion

How to point to a CDL netlist in my config view

Category: Custom IC Design

By Svilen64

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updated over 3 years ago by Andrew Beckett

1 replies • 10703 views
Discussion

Access Top-Level Hierarchical Net with BSource

Category: Custom IC Design

By FormerMember

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updated over 3 years ago by Andrew Beckett

1 replies • 4039 views
Discussion

Power calculation

Category: Custom IC Design

By abdurrahman0234

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updated over 3 years ago by Andrew Beckett

1 replies • 10486 views
Discussion

Performing AMS simulation in cadence virtuoso, the voltage value printed out exceeds the set power supply voltage value

Category: Custom IC Design

By zuiying

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updated over 3 years ago by Andrew Beckett

1 replies • 12024 views
Discussion

CalcVal cannot pass the output of previous run to the next run on simulation using Run Plan.

Category: Custom IC Design

By delgsy

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updated over 3 years ago by Andrew Beckett

5 replies • 13071 views
Discussion

Voltage controlled Current source (VCCS) for ideal OTA

Category: Custom IC Design

By Charanraj Mohan

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updated over 3 years ago by Andrew Beckett

3 replies • 17383 views
Discussion

How can I use statistical results, e.g., mean, standard deviation, from previous test as design (or global) variable of the current test?

Category: Custom IC Design

By delgsy

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updated over 3 years ago by Andrew Beckett

3 replies • 12579 views

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