Custom IC Design

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Spectre TRAN noise analysis ends with memory fault after warning: (SPECTRE-16780): LTE tolerance was temporarily relaxed to step over a discontinuity in the signal:

Category: Custom IC Design

By vivkr

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updated over 12 years ago by Andrew Beckett

4 replies • 18725 views
Discussion

PDK Installed but doesn't show in CIW

Category: Custom IC Design

By wgtkan

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updated over 12 years ago by Andrew Beckett

1 replies • 2594 views
Discussion

How to measure gm accurately

Category: Custom IC Design

By wgtkan

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updated over 12 years ago by Andrew Beckett

1 replies • 19261 views
Discussion

How to plot an histogram using ocean script? (monte carlo problem)

Category: Custom IC Design

By Ricardo Alves

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updated over 12 years ago by Andrew Beckett

1 replies • 14721 views
Discussion

ADE-L progress bar during ac, noise or stb analyses disturbs cadence environment. How to switch it off?

Category: Custom IC Design

By dalistoj

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updated over 12 years ago by Andrew Beckett

1 replies • 13646 views
Discussion

How to simulate starRC generated .SPF files through ADE

Category: Custom IC Design

By reddy1553

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updated over 12 years ago by Andrew Beckett

3 replies • 19323 views
Discussion

ADE XL multiple tests with different corners

Category: Custom IC Design

By Tobben24

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updated over 12 years ago by Andrew Beckett

1 replies • 16282 views
Discussion

Using ocean ADEXL generate a csv output file

Category: Custom IC Design

By rkic

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updated over 12 years ago by Andrew Beckett

7 replies • 19671 views
Discussion

How to associate an extracted netlist of a subckt to the symbol view in schematic editor.

Category: Custom IC Design

By RFStuff

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updated over 12 years ago by RFStuff

8 replies • 21221 views
Discussion

Huge psf file!! Cannot allocate memory

Category: Custom IC Design

By SPA1984

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updated over 12 years ago by Andrew Beckett

3 replies • 16591 views
Discussion

How to load my configeration files from my working directory not home directory

Category: Custom IC Design

By wgtkan

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updated over 12 years ago by wgtkan

4 replies • 19126 views
Discussion

Doubt regarding layout gpdk 45nm

Category: Custom IC Design

By madhusudha

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updated over 12 years ago by theopaone

2 replies • 19433 views
Discussion

Cadence waveform viewer display error

Category: Custom IC Design

By likelike

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updated over 12 years ago by likelike

2 replies • 16128 views
Discussion

Operating Region Spec

Category: Custom IC Design

By Tobben24

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updated over 12 years ago by Andrew Beckett

1 replies • 14920 views
Discussion

ADEXL and VerilogA

Category: Custom IC Design

By Tobben24

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updated over 12 years ago by Tobben24

2 replies • 13960 views

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