Custom IC Design

Latest Posts

Discussion

Export simulation results in excel file

Category: Custom IC Design

By Holz
•
updated over 4 years ago by Holz

2 replies • 11379 views
Discussion

Removing mouse auto default to "Ok" in pop up dialogue within Virtuoso

Category: Custom IC Design

By blankman
•
updated over 4 years ago by Frank Wiedmann

2 replies • 1390 views
Discussion

How much storage does a single simulation use?

Category: Custom IC Design

By Holz
•
updated over 4 years ago by Holz

2 replies • 9996 views
Discussion

ADE Assembler Message 1921 - When running multiple sweep points

Category: Custom IC Design

By Christos Skoufis
•
updated over 4 years ago by Christos Skoufis

6 replies • 7799 views
Discussion

recognize paths with metal jumps using DIVA

Category: Custom IC Design

By strotta
•
updated over 4 years ago by Andrew Beckett

1 replies • 9672 views
Discussion

Mu and Mu_prime in S parameter analysis

Category: Custom IC Design

By Abhinav2020
•
updated over 4 years ago by Frank Wiedmann

4 replies • 15382 views
Discussion

How can you move/stretch schematic wires WITHOUT Virtuoso rerouting everything and making a mess?

Category: Custom IC Design

By CADcasualty
•
updated over 4 years ago by mmsaad66

2 replies • 5096 views
Discussion

Transient stop time for specified number of clocks

Category: Custom IC Design

By Senan
•
updated over 4 years ago by Andrew Beckett

7 replies • 14027 views
Discussion

How to flatten GDS by stream out or Command

Category: Custom IC Design

By MollyMeow
•
updated over 4 years ago by MollyMeow

2 replies • 10755 views
Discussion

Environment variable questions

Category: Custom IC Design

By sjwprcker
•
updated over 4 years ago by sjwprcker

2 replies • 10426 views
Discussion

Simulating with a Calibre Extracted Netlist with ADE Explorer

Category: Custom IC Design

By jshumble
•
updated over 4 years ago by jshumble

3 replies • 12488 views
Discussion

pstb analysis shows different results at different iprobe position

Category: Custom IC Design

By Irenexox
•
updated over 4 years ago by FormerMember

1 replies • 12014 views
Discussion

Sort function to sort the paths selected using the bbox or beginpt or end pt

Category: Custom IC Design

By kumargbn
•
updated over 4 years ago by kumargbn

2 replies • 10690 views
Discussion

How to detect EOF with Verilog-ams fscanf?

Category: Custom IC Design

By Martinsh
•
started over 4 years ago

0 replies • 10145 views
Discussion

Generating data in csv format from netlist simulation

Category: Custom IC Design

By sidm
•
updated over 4 years ago by Andrew Beckett

3 replies • 10726 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.