Custom IC Design

Latest Posts

Discussion

Not able add pins to symbol; restricted by string length

Category: Custom IC Design

By ajmr
•
updated over 4 years ago by ajmr

4 replies • 10526 views
Discussion

Greyed menu: "Run Assura Quantus QRC..." and "Run Assura Quantus QRC..."

Category: Custom IC Design

By manudupouy
•
updated over 4 years ago by WenhaoY

35 replies • 23480 views
Discussion

Convert Digital Bus to an Integer value - Calculator Viva

Category: Custom IC Design

By FAwqati
•
updated over 4 years ago by abdurrahman0234

10 replies • 19565 views
Discussion

Reduce the spacing between metals while placing stack auto via.

Category: Custom IC Design

By skillEater
•
updated over 4 years ago by chanho

7 replies • 16516 views
Discussion

ViVA Customization using .cdsinit

Category: Custom IC Design

By hoodskier
•
updated over 4 years ago by Andrew Beckett

10 replies • 21393 views
Discussion

Getting data from an "intersect"

Category: Custom IC Design

By CSCNalu
•
updated over 4 years ago by FormerMember

6 replies • 3889 views
Discussion

if statement in ade xl

Category: Custom IC Design

By Holz
•
updated over 4 years ago by Holz

3 replies • 15789 views
Discussion

Can I start a simulation in the mid night?

Category: Custom IC Design

By ichiro
•
updated over 4 years ago by Andrew Beckett

1 replies • 9930 views
Discussion

ADE XL Not including Spectre Models

Category: Custom IC Design

By Zachary Nelson
•
updated over 4 years ago by Andrew Beckett

5 replies • 11252 views
Discussion

I had an error of "matrix is singular" only by APS.

Category: Custom IC Design

By ichiro
•
updated over 4 years ago by ichiro

2 replies • 1499 views
Discussion

Question about AC simulation with verilog-A model

Category: Custom IC Design

By dskang
•
updated over 4 years ago by dskang

1 replies • 10555 views
Discussion

AGPDK cds_ff_mpt_v_1.0

Category: Custom IC Design

By Vamshi S K
•
updated over 4 years ago by Andrew Beckett

1 replies • 10278 views
Discussion

Generating .lib file for synthesis using Genus from transistor level cells using Virtuoso

Category: Custom IC Design

By iamKarthikBK
•
updated over 4 years ago by Guangjun Cao

28 replies • 30719 views
Discussion

compare two netlists

Category: Custom IC Design

By sjwprcker
•
updated over 4 years ago by MaximX

3 replies • 14944 views
Discussion

Assura doesn't recognise pins generated from sources

Category: Custom IC Design

By iamKarthikBK
•
updated over 4 years ago by iamKarthikBK

5 replies • 2668 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.