Custom IC Design

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Discussion

How to convert a technology file to a layer mapping file

Category: Custom IC Design

By SUEE

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updated over 12 years ago by SUEE

5 replies • 21747 views
Discussion

strange error message in running adexl

Category: Custom IC Design

By Joe Black

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updated over 12 years ago by Andrew Beckett

8 replies • 19882 views
Discussion

vdbToRcx error

Category: Custom IC Design

By wighou

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updated over 12 years ago by Andrew Beckett

3 replies • 14308 views
Discussion

Parameter Measurements

Category: Custom IC Design

By madhusudha

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updated over 12 years ago by Andrew Beckett

1 replies • 14248 views
Discussion

functional error

Category: Custom IC Design

By gsciller

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updated over 12 years ago by Andrew Beckett

1 replies • 13681 views
Discussion

Licensing problem for QRC extraction

Category: Custom IC Design

By wighou

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updated over 12 years ago by Andrew Beckett

2 replies • 14533 views
Discussion

Assigning a Net Name to a Layer for LVS/RCX

Category: Custom IC Design

By LanceT

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updated over 12 years ago by Andrew Beckett

7 replies • 3476 views
Discussion

Layout cell checked out warnings because of rulers.

Category: Custom IC Design

By fun4skilled

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updated over 12 years ago by Andrew Beckett

4 replies • 14413 views
Discussion

How to get the windowId?

Category: Custom IC Design

By Siddique baig

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updated over 12 years ago by Siddique baig

2 replies • 18546 views
Discussion

AMS Simulator support for SystemVerilog Math Functions

Category: Custom IC Design

By gintel

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updated over 12 years ago by gintel

2 replies • 16094 views
Discussion

Loosening tolerance on a subcircuit basis

Category: Custom IC Design

By swdesigner

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updated over 12 years ago by Andrew Beckett

1 replies • 13540 views
Discussion

Referencing symbols with buses during SpiceIn

Category: Custom IC Design

By brianzimmer

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started over 12 years ago

0 replies • 13627 views
Discussion

Information on dc_pivot_check option

Category: Custom IC Design

By Dmitry Babin

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updated over 12 years ago by Dmitry Babin

4 replies • 24687 views
Discussion

How do I get ADEXL to update and fill in missing MonteCarlo trials that failed to converge?

Category: Custom IC Design

By billnxp

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started over 12 years ago

0 replies • 13542 views
Discussion

Pin mismatch between schematic and symbol in Virtuoso

Category: Custom IC Design

By asta51

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updated over 12 years ago by Andrew Beckett

1 replies • 16280 views

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