Custom IC Design

Latest Posts

Discussion

How does the correlation constraint "cc" affect the correlation of mismatch parameters

Category: Custom IC Design

By Matthew CG

$usertype
•
updated over 4 years ago by Matthew CG

2 replies • 2396 views
Discussion

Models for components in sample lib

Category: Custom IC Design

By sidm

$usertype
•
updated over 4 years ago by sidm

6 replies • 12802 views
Discussion

Change default increment of deriv

Category: Custom IC Design

By Holz

$usertype
•
updated over 4 years ago by FormerMember

5 replies • 11472 views
Discussion

How can I import verilog-A (.va) file in the cadence virtuoso?

Category: Custom IC Design

By yysunj

$usertype
•
updated over 4 years ago by Andrew Beckett

1 replies • 10904 views
Discussion

PLL reference model for PSS+PNOISE

Category: Custom IC Design

By HoWei

$usertype
•
updated over 4 years ago by FormerMember

5 replies • 4444 views
Discussion

Maestro - use other output as spec value.

Category: Custom IC Design

By JeyJey

$usertype
•
updated over 4 years ago by JeyJey

6 replies • 4834 views
Discussion

How to plot current results along with last run results in the same window/tab in viva.

Category: Custom IC Design

By kenc184

$usertype
•
updated over 4 years ago by kenc184

4 replies • 4731 views
Discussion

write *.scs file to use model library

Category: Custom IC Design

By mirtaji65

$usertype
•
updated over 4 years ago by mirtaji65

2 replies • 12640 views
Discussion

Stimulating an internal node from a higher hierarchy level

Category: Custom IC Design

By Johanny Saenz

$usertype
•
updated over 4 years ago by Andrew Beckett

5 replies • 11700 views
Discussion

Running Monte Carlo simulations on a statistical corner in ADE XL

Category: Custom IC Design

By ddsab

$usertype
•
updated over 4 years ago by Andrew Beckett

3 replies • 16730 views
Discussion

Joining a line between two points on the output waveform in Cadence Virtuoso calculator tool

Category: Custom IC Design

By Senan

$usertype
•
updated over 4 years ago by Senan

2 replies • 11730 views
Discussion

DC operating point for different analyses

Category: Custom IC Design

By Banai

$usertype
•
updated over 4 years ago by Banai

4 replies • 15510 views
Discussion

Parasitic extraction tools for Cadence

Category: Custom IC Design

By omiya

$usertype
•
updated over 4 years ago by omiya

2 replies • 12866 views
Discussion

how to add printf statement to .cdsenv file?

Category: Custom IC Design

By KurtKimber1

$usertype
•
updated over 4 years ago by KurtKimber1

4 replies • 10791 views
Discussion

Print Noise summary and corresponding OCEAN noiseSummary

Category: Custom IC Design

By AncisMichele

$usertype
•
updated over 4 years ago by AncisMichele

15 replies • 16999 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.