Custom IC Design

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Discussion

Guidelines for the Custom IC Design Forum

Category: Custom IC Design

By Andrew Beckett

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started over 14 years ago

0 replies • 29473 views
Discussion

Cadence Virtuoso IC6.1.8 - Layout GXL Automatic Placement

Category: Custom IC Design

By hoangtn3702

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started 4 hours ago

0 replies • 21 views
Discussion

Fundamental question on edge phase noise from sampled PNOISE

Category: Custom IC Design

By Yuto Lau

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updated 4 hours ago by Yuto Lau

4 replies • 174 views
Discussion

Virtuoso AMS NOUNIT error with Xcelium - Not caching libraries

Category: Custom IC Design

By AS202502163432

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updated 9 hours ago by AS202502163432

2 replies • 107 views
Discussion

Query regarding Virtuoso EMX tool

Category: Custom IC Design

By VLSI lab IITB

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updated 10 hours ago by Saloni Chhabra

1 replies • 54 views
Discussion

Assembler: possible to force inclusion of model file(s) at the very beginning of netlist?

Category: Custom IC Design

By dontpanic

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updated 11 hours ago by Saloni Chhabra

1 replies • 101 views
Discussion

wait a long time to have results updated

Category: Custom IC Design

By sjwprcssw

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started 1 day ago

0 replies • 53 views
Discussion

SOA analysis in cadence virtuoso

Category: Custom IC Design

By TUKA

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started 2 days ago

0 replies • 68 views
Discussion

Strategy for Accelerating Full-Chip AMS Simulation with Multi-Rate Clocks (1kHz / 100MHz)

Category: Custom IC Design

By HY202510149941

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updated 2 days ago by Alonso Schmidt

1 replies • 189 views
Discussion

Buses in spectreText when creating symbol

Category: Custom IC Design

By MC20250412421

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updated 3 days ago by MC20250412421

2 replies • 210 views
Discussion

Replace symbol pin names without changing the pin placement and symbol boundary

Category: Custom IC Design

By SimhanAnalog

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updated 6 days ago by Andrew Beckett

2 replies • 367 views
Discussion

Does Cadence provide a standard Python API for tool automation?

Category: Custom IC Design

By WM20250906725

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updated 6 days ago by Andrew Beckett

5 replies • 2041 views
Discussion

Issue with Skywater 130 Monte Carlo Mismatch Analysis

Category: Custom IC Design

By VLSI lab IITB

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updated 7 days ago by VLSI lab IITB

2 replies • 331 views
Discussion

Issue with the ADE Explorer/Assembler simulator

Category: Custom IC Design

By GL202502244954

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started 7 days ago

0 replies • 121 views
Discussion

Date/time (or $system) in verilogA

Category: Custom IC Design

By leok

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updated 9 days ago by leok

2 replies • 154 views

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