Custom IC Design

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Discussion

how to setup and run multiple STB simulation in a single state

Category: Custom IC Design

By Pic Hao

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updated over 6 years ago by sjwprc

2 replies • 18189 views
Discussion

寄生参数提取之后进行spectre仿真出错

Category: Custom IC Design

By langj17

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updated over 6 years ago by sjwprc

1 replies • 14415 views
Discussion

square pin in schematic

Category: Custom IC Design

By zssfred

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updated over 6 years ago by zssfred

2 replies • 14101 views
Discussion

[Virtuoso]Can I get SPICE model parameters of MOSFETs in library?

Category: Custom IC Design

By Leey

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updated over 6 years ago by Frank Wiedmann

2 replies • 8081 views
Discussion

Pegasus LVS GUI to Load last selected Rule Set

Category: Custom IC Design

By hchan

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started over 6 years ago

0 replies • 13161 views
Discussion

VSR multi-level auto routing

Category: Custom IC Design

By henriqueiesam

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started over 6 years ago

0 replies • 13155 views
Discussion

Timestamp warning when using ADE Assembler (Maestro)

Category: Custom IC Design

By HoWei

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started over 6 years ago

0 replies • 13001 views
Discussion

How to check simulation time of block ?

Category: Custom IC Design

By Asako

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started over 6 years ago

0 replies • 13009 views
Discussion

define specs in adexl in text editor or batch mode? or batch tool for checking vdsat and vsat_margin?

Category: Custom IC Design

By monglebest

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updated over 6 years ago by monglebest

2 replies • 13738 views
Discussion

Using multiple dynamic parameters when one is a variable

Category: Custom IC Design

By DouglasAH

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updated over 6 years ago by DouglasAH

4 replies • 16490 views
Discussion

Making schematic from layout

Category: Custom IC Design

By suchende

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started over 6 years ago

0 replies • 12749 views
Discussion

Dotted lines by default in ViVA

Category: Custom IC Design

By BaaB

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updated over 6 years ago by Andrew Beckett

14 replies • 24269 views
Discussion

Standard Cell Library Integration

Category: Custom IC Design

By DrM1ller

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updated over 6 years ago by Andrew Beckett

1 replies • 13952 views
Discussion

Schematic returns to most upper level when click Main Form or Transient Signal

Category: Custom IC Design

By BaaB

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updated over 6 years ago by BaaB

4 replies • 13702 views
Discussion

deepprobe to a bussed net in AMS

Category: Custom IC Design

By paguirre78

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updated over 6 years ago by paguirre78

5 replies • 20182 views

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