Custom IC Design

Latest Posts

Discussion

How is the netlisting done in ADE

Category: Custom IC Design

By anoopvk

$usertype
•
updated over 7 years ago by Andrew Beckett

1 replies • 13900 views
Discussion

need document regarding voltage sources and it usage (vdc, vpulse..etc)

Category: Custom IC Design

By AARORA

$usertype
•
updated over 7 years ago by Andrew Beckett

1 replies • 13880 views
Discussion

ADE XL Job Policy Setup -> Max. Jobs - automatic set after start

Category: Custom IC Design

By AndreyVolk

$usertype
•
updated over 7 years ago by AndreyVolk

1 replies • 4848 views
Discussion

noise analysis during transient

Category: Custom IC Design

By nicola91it

$usertype
•
updated over 7 years ago by nicola91it

2 replies • 13614 views
Discussion

[IC6.1.7] Simulating VHDL-AMS

Category: Custom IC Design

By LukiLeu

$usertype
•
updated over 7 years ago by LukiLeu

2 replies • 14615 views
Discussion

What is the difference between the $PATH variables?

Category: Custom IC Design

By AndreyVolk

$usertype
•
updated over 7 years ago by AndreyVolk

2 replies • 6717 views
Discussion

variable $freq in veriloga

Category: Custom IC Design

By RobinCommander

$usertype
•
updated over 7 years ago by Frank Wiedmann

6 replies • 17806 views
Discussion

saving results with same net names of two different cells

Category: Custom IC Design

By EngrZM

$usertype
•
updated over 7 years ago by Andrew Beckett

3 replies • 13815 views
Discussion

Number of accepted tran steps in spectre log

Category: Custom IC Design

By anoopvk

$usertype
•
updated over 7 years ago by Andrew Beckett

1 replies • 14143 views
Discussion

Modifying an extracted view for post layout simulation.

Category: Custom IC Design

By ghrshomali

$usertype
•
updated over 7 years ago by Bruce A

16 replies • 24365 views
Discussion

Dynamically Changing the pulse width - vpulse/vsource

Category: Custom IC Design

By vijaykpd

$usertype
•
updated over 7 years ago by vijaykpd

4 replies • 8330 views
Discussion

How to tell spectre (in ADE L) to enable "monte carlo" mode

Category: Custom IC Design

By itos

$usertype
•
updated over 7 years ago by Andrew Beckett

1 replies • 2564 views
Discussion

ADEXL: Making Dependent Tests

Category: Custom IC Design

By BrJaWr

$usertype
•
updated over 7 years ago by Andrew Beckett

8 replies • 23344 views
Discussion

Simulation with verilog-a model

Category: Custom IC Design

By HANNN

$usertype
•
updated over 7 years ago by Andrew Beckett

3 replies • 16923 views
Discussion

Assura DRC doesn't zoom to errors

Category: Custom IC Design

By spaceradlab

$usertype
•
updated over 7 years ago by Andrew Beckett

1 replies • 1192 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.