Custom IC Design

Latest Posts

Discussion

Assura LVS fail

Category: Custom IC Design

By Campo85
•
updated over 13 years ago by Quek

6 replies • 17897 views
Discussion

Single Electron Transistor Simulation

Category: Custom IC Design

By RAJ JOHRI
•
updated over 13 years ago by Quek

1 replies • 13117 views
Discussion

Measurement of Charge of Capacitor

Category: Custom IC Design

By RAJ JOHRI
•
started over 13 years ago

0 replies • 13121 views
Discussion

IC614 issues with $DISPLAY

Category: Custom IC Design

By tkhan
•
updated over 13 years ago by tkhan

8 replies • 16715 views
Discussion

Skill code for extracting wire information for one signal

Category: Custom IC Design

By MYIN
•
updated over 13 years ago by skillUser

3 replies • 13835 views
Discussion

Some weird things going on with properties in Layout

Category: Custom IC Design

By Kabal
•
updated over 13 years ago by Kabal

1 replies • 12815 views
Discussion

ErcChk segmentation fault

Category: Custom IC Design

By mlxsae
•
updated over 13 years ago by Quek

1 replies • 13540 views
Discussion

Matlab RF/Spectre Toolbox

Category: Custom IC Design

By BoulderDash
•
updated over 13 years ago by nevinalex1234

5 replies • 3869 views
Discussion

Importing verilog to Cadence schematic

Category: Custom IC Design

By Wonyoung
•
updated over 13 years ago by weebey

10 replies • 21286 views
Discussion

IC5141_USR6 in RHEL5

Category: Custom IC Design

By Satya
•
updated over 13 years ago by DanL

8 replies • 14361 views
Discussion

Is it possible to convert layout.oa/sch.oa database format to text

Category: Custom IC Design

By ramiabr
•
updated over 13 years ago by Quek

1 replies • 1990 views
Discussion

spectre

Category: Custom IC Design

By arundevnkumar
•
updated over 13 years ago by Quek

1 replies • 12759 views
Discussion

setting snapMode to anyAngle in Virtuoso 6.1.5 using env var (SOLVED)

Category: Custom IC Design

By MOSFET
•
updated over 13 years ago by Andrew Beckett

2 replies • 14315 views
Discussion

Defining length in an expression to be evaluated

Category: Custom IC Design

By canbaltaci
•
updated over 13 years ago by Andrew Beckett

3 replies • 13649 views
Discussion

How to compile verilog file to valid IC6.x cellview from command prompt

Category: Custom IC Design

By aleksand1975
•
updated over 13 years ago by aleksand1975

2 replies • 13564 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.