Custom IC Design

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Interactive mode for Spectre using Python/TCL

Category: Custom IC Design

By CB202409064221

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updated 2 months ago by Andrew Beckett

1 replies • 444 views
Discussion

PAC is giving 0V at the output

Category: Custom IC Design

By SA202512302438

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updated 2 months ago by Frank Wiedmann

2 replies • 1098 views
Discussion

Replace symbol pin names without changing the pin placement and symbol boundary

Category: Custom IC Design

By SimhanAnalog

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updated 3 months ago by SimhanAnalog

4 replies • 1741 views
Discussion

Which simulation tools are supported for Voltus-XFi within Virtuoso environment?

Category: Custom IC Design

By JY202510312553

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started 3 months ago

0 replies • 787 views
Discussion

TSMC PDK Inductor Finder

Category: Custom IC Design

By nqthang

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started 3 months ago

0 replies • 1049 views
Discussion

Fundamental question on edge phase noise from sampled PNOISE

Category: Custom IC Design

By Yuto Lau

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updated 3 months ago by Yuto Lau

6 replies • 1600 views
Discussion

PWM block gain simulation using pss

Category: Custom IC Design

By TH202510293247

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started 3 months ago

0 replies • 680 views
Discussion

Cadence Virtuoso IC6.1.8 - Layout GXL Automatic Placement

Category: Custom IC Design

By hoangtn3702

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started 3 months ago

0 replies • 284 views
Discussion

wait a long time to have results updated

Category: Custom IC Design

By sjwprcssw

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started 3 months ago

0 replies • 822 views
Discussion

SOA analysis in cadence virtuoso

Category: Custom IC Design

By TUKA

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started 3 months ago

0 replies • 925 views
Discussion

Strategy for Accelerating Full-Chip AMS Simulation with Multi-Rate Clocks (1kHz / 100MHz)

Category: Custom IC Design

By HY202510149941

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updated 3 months ago by Alonso Schmidt

1 replies • 1107 views
Discussion

Buses in spectreText when creating symbol

Category: Custom IC Design

By MC20250412421

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updated 3 months ago by MC20250412421

2 replies • 1149 views
Discussion

Does Cadence provide a standard Python API for tool automation?

Category: Custom IC Design

By WM20250906725

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updated 3 months ago by Andrew Beckett

5 replies • 4074 views
Discussion

Issue with the ADE Explorer/Assembler simulator

Category: Custom IC Design

By GL202502244954

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started 3 months ago

0 replies • 331 views
Discussion

Date/time (or $system) in verilogA

Category: Custom IC Design

By leok

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updated 3 months ago by leok

2 replies • 585 views

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