Custom IC Design

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Discussion

python script which can connect with virtuoso

Category: Custom IC Design

By AG20250626213
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started 2 months ago

0 replies • 619 views
Discussion

Probing current of an instance using hidden supply pins

Category: Custom IC Design

By Volker T
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updated 2 months ago by Volker T

1 replies • 736 views
Discussion

How to prevent parameter updates for pending simulations during ADEXL simulation

Category: Custom IC Design

By dogman4
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updated 2 months ago by dogman4

10 replies • 1435 views
Discussion

adexl's "Run Simulation" always hidden when first open

Category: Custom IC Design

By dogman4
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updated 2 months ago by dogman4

3 replies • 430 views
Discussion

Function to Detect Minimum Pulse Width

Category: Custom IC Design

By Kevin T Buck
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updated 2 months ago by Kevin T Buck

1 replies • 786 views
Discussion

Problem with Liberate and Verilog-A Model

Category: Custom IC Design

By FM202408077836
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updated 2 months ago by FM202408077836

2 replies • 1213 views
Discussion

Layout: Edit-in Place -> show full layer palette

Category: Custom IC Design

By PK202501238151
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updated 2 months ago by PK202501238151

2 replies • 449 views
Discussion

Wprobe - Power/PAE calculation in Envelope Wireless analysis

Category: Custom IC Design

By UbltSR
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started 2 months ago

0 replies • 231 views
Discussion

Library Manager: Can it support e.g. bitmap pictures and libre office documents?

Category: Custom IC Design

By StephanWeber
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updated 2 months ago by henker

1 replies • 863 views
Discussion

How to define Cell based on S-Parameters

Category: Custom IC Design

By spatz
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updated 2 months ago by Saloni Chhabra

3 replies • 1088 views
Discussion

View list and Stop list in Cadence PVS

Category: Custom IC Design

By thiruvenkata
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updated 2 months ago by ilyaF

4 replies • 1335 views
Discussion

Hierarchical LVS Issues or how to deal with LVS hierarchy

Category: Custom IC Design

By spatz
•
updated 2 months ago by RobMan

3 replies • 1181 views
Discussion

Different PSS and Pnoise result with different Fund and sample_ratio settings

Category: Custom IC Design

By YutaoLiu
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started 3 months ago

0 replies • 834 views
Discussion

The tran+stb simulation phase curve declines from -150 degree

Category: Custom IC Design

By liangqunshan
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updated 3 months ago by liangqunshan

1 replies • 410 views
Discussion

Check and Asserts in Monte-Carlo

Category: Custom IC Design

By lagoud
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updated 3 months ago by KV202505288952

5 replies • 2125 views

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