Custom IC Design

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Guidance on reducing RLCK extraction size for PDN inductance analysis (Quantus PVS)

Category: Custom IC Design

By baltaci
•
started 5 months ago

0 replies • 494 views
Discussion

Memory usage during simulation

Category: Custom IC Design

By dogman4
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updated 5 months ago by Andrew Beckett

5 replies • 1233 views
Discussion

bindkeys of library manager

Category: Custom IC Design

By dogman4
•
updated 5 months ago by Andrew Beckett

1 replies • 672 views
Discussion

Opening layout takes long time after relaunching virtuoso or closing all data

Category: Custom IC Design

By MM20260514770
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updated 5 months ago by Andrew Beckett

1 replies • 704 views
Discussion

Density command query related to Pegasus.

Category: Custom IC Design

By SB202511198144
•
started 5 months ago

0 replies • 444 views
Discussion

Potential Simulator Artifacts: Glitches in Isolated Blocks during Transient Analysis

Category: Custom IC Design

By SpiceMonkey
•
updated 5 months ago by Andrew Beckett

1 replies • 654 views
Discussion

How to make stack for transistor

Category: Custom IC Design

By RM202605273230
•
updated 5 months ago by RM202605273230

11 replies • 2869 views
Discussion

Modify Assembler Max Jobs on Frozen Virtuoso

Category: Custom IC Design

By dogman4
•
updated 5 months ago by dogman4

2 replies • 764 views
Discussion

How to adjust the brightness of grid lines in the layout interface

Category: Custom IC Design

By JH202504237643
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updated 5 months ago by Andrew Beckett

3 replies • 1047 views
Discussion

DC nested sweep of variables

Category: Custom IC Design

By Svilen64
•
updated 6 months ago by Svilen64

16 replies • 5825 views
Discussion

Verilog Parsing Fails

Category: Custom IC Design

By OOMR
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updated 6 months ago by Andrew Beckett

1 replies • 1086 views
Discussion

spectre nodes info: pin names different than what is in schematic or input.scs

Category: Custom IC Design

By marcelpreda
•
updated 6 months ago by marcelpreda

3 replies • 1840 views
Discussion

How to use getData() without hardcoded results path, for a DC sweep?

Category: Custom IC Design

By dontpanic
•
updated 6 months ago by Andrew Beckett

2 replies • 1339 views
Discussion

How to obtain the poles and zeros of loop gain in PZ simulation

Category: Custom IC Design

By YG202604287552
•
updated 6 months ago by Andrew Beckett

1 replies • 1164 views
Discussion

Combining multiple calculator outputs into a vector/bus in Virtuoso Assembler

Category: Custom IC Design

By baltaci
•
updated 6 months ago by JankoK

1 replies • 990 views

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