i am working with soc -encounter. while routing the design no violations were reported.but when verified with calibre -lvs its showing 4 incomplete nets. when checked for same nets in soc - E those are no connected/routed as required.what would be the reason & how to overcome such violations.
should these nets must be routed manually?
Yes , route them manually
If you run Verify Connectivity in Encounter do these nets get reported as open? If they do, NanoRoute should route them assuming they are signal nets and they have not been excluded from routing (setAttribute -net netName -skip_routing true). If Verify Connectivity does not report the open then double check that the Verilog netlist defines the connectivity. If these are power/ground nets make sure globalNetConnect was run to define their connectivity and use power planning commands (addRing, addStripe, sroute) to route them.
Verify Connectivity does not report any violations. When taken to calibre for LVS, these nets are reported as incomplete.
When checked back in SoC-E these are not connected as intended.
These are not power/ground nets.
what does one of these nets look like in the verilog or def?
try running verify connectivity on the specific net name.
not sure what's going on, just some ideas to try...
Thanks for your suggestions, finaly found out the reason behind the problem.
The netlist provided was not made case-sensitive. In design which were reported as incomplete nets are all case senstive.
This we can found out by checking in Tools --> schematic viewer of SoC-E.
When i tried it showed 2 nets of same name with case sensitivity like N97 & n97. By making the netlist case sensitive the problem is solved.