Digital Implementation

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Discussion

Xtensa TIE documentation

Category: Digital Implementation

By ciapata
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started over 2 years ago

0 replies • 5991 views
Discussion

No buffers added in power domain, hold violation

Category: Digital Implementation

By Krippkrupp
•
updated over 2 years ago by Krippkrupp

3 replies • 7165 views
Discussion

Cadence Modus generated test pattens

Category: Digital Implementation

By hpriya
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started over 2 years ago

0 replies • 5667 views
Discussion

could not find lookup table definition

Category: Digital Implementation

By Rameen
•
started over 2 years ago

0 replies • 5300 views
Discussion

Voltus: How to validate which qrc techfile is used during tool top-level power grid extraction

Category: Digital Implementation

By Hieu Hoang
•
started over 2 years ago

0 replies • 5509 views
Discussion

Voltus: WARNING IMPEXT-2773

Category: Digital Implementation

By Hieu Hoang
•
started over 2 years ago

0 replies • 5328 views
Discussion

Spare cells are outside their region/fence

Category: Digital Implementation

By Domi Hammerfall
•
started over 2 years ago

0 replies • 896 views
Discussion

Instance grid not aligned to core sites due to automatic changes on the floorplan made by Innovus

Category: Digital Implementation

By Domi Hammerfall
•
started over 2 years ago

0 replies • 6288 views
Discussion

xt-ld.exe cannot find CMSIS DSP library

Category: Digital Implementation

By aravindt
•
updated over 2 years ago by vsydoruk

5 replies • 7939 views
Discussion

Convergence issue while simulating CNTFET adder

Category: Digital Implementation

By Aalelai
•
updated over 2 years ago by Aalelai

2 replies • 6625 views
Discussion

How to prevent sroute from placing vias where there already are some?

Category: Digital Implementation

By Domi Hammerfall
•
updated over 2 years ago by Domi Hammerfall

2 replies • 6502 views
Discussion

Are the -add and -master_clock constraints needed in an MMMC setup?

Category: Digital Implementation

By Domi Hammerfall
•
updated over 2 years ago by DimoM

3 replies • 1984 views
Discussion

How to resolve clock gating hold checks (nets could not be fixed because it is clock net)?

Category: Digital Implementation

By Domi Hammerfall
•
updated over 2 years ago by DimoM

12 replies • 17006 views
Discussion

Cadence genus synthesis

Category: Digital Implementation

By Jeeva96
•
updated over 2 years ago by DimoM

1 replies • 7737 views
Discussion

Innovus vs Calibre DRC results

Category: Digital Implementation

By Anas2023a95
•
updated over 2 years ago by DimoM

3 replies • 9822 views

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