Digital Implementation

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Discussion

How do I exclude specific cells of the library?

Category: Digital Implementation

By rangas

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started over 2 years ago

0 replies • 5727 views
Discussion

Power estimation of combinational logic design in Genus

Category: Digital Implementation

By SaranyaBalan

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started over 2 years ago

0 replies • 5946 views
Discussion

The .def file after placement stage

Category: Digital Implementation

By PacificFeng

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started over 2 years ago

0 replies • 5807 views
Discussion

innovus placement related issue

Category: Digital Implementation

By PacificFeng

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updated over 2 years ago by PacificFeng

2 replies • 7469 views
Discussion

AI affects

Category: Digital Implementation

By Andrew018

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started over 2 years ago

0 replies • 5384 views
Discussion

Verilog netlist to Schematics

Category: Digital Implementation

By Anas2023a95

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updated over 2 years ago by Andrew018

1 replies • 9224 views
Discussion

Using the generic PDK with Genus

Category: Digital Implementation

By peck

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started over 2 years ago

0 replies • 7003 views
Discussion

*** CRASHED *** [signal 11] Segmentation fault (core dumped) invoking tempus

Category: Digital Implementation

By Neubee

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started over 2 years ago

0 replies • 6321 views
Discussion

Large difference between post-route and signoff timing despite up-to-date RC scaling factors

Category: Digital Implementation

By Domi Hammerfall

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updated over 2 years ago by Domi Hammerfall

2 replies • 9127 views
Discussion

Xtensa TIE documentation

Category: Digital Implementation

By ciapata

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started over 2 years ago

0 replies • 6741 views
Discussion

No buffers added in power domain, hold violation

Category: Digital Implementation

By Krippkrupp

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updated over 2 years ago by Krippkrupp

3 replies • 8143 views
Discussion

Cadence Modus generated test pattens

Category: Digital Implementation

By hpriya

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started over 2 years ago

0 replies • 6477 views
Discussion

could not find lookup table definition

Category: Digital Implementation

By Rameen

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started over 2 years ago

0 replies • 5995 views
Discussion

Voltus: How to validate which qrc techfile is used during tool top-level power grid extraction

Category: Digital Implementation

By Hieu Hoang

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started over 2 years ago

0 replies • 6248 views
Discussion

Voltus: WARNING IMPEXT-2773

Category: Digital Implementation

By Hieu Hoang

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started over 2 years ago

0 replies • 6007 views

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