Digital Implementation

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Discussion

clkgate setup timing violation is not treated by optDesign

Category: Digital Implementation

By greenblat
•
updated over 15 years ago by Kari

3 replies • 15483 views
Discussion

Encounter RTL-to-GDSII System 10.1 timing library include

Category: Digital Implementation

By vvijendr
•
updated over 15 years ago by Kari

1 replies • 14558 views
Discussion

Current net list does not match wires file

Category: Digital Implementation

By raj7783
•
updated over 15 years ago by raj7783

1 replies • 14353 views
Discussion

Encounter-verify geometry:SameNet violation

Category: Digital Implementation

By erin168
•
updated over 15 years ago by erin168

1 replies • 1802 views
Discussion

MMMC CTS

Category: Digital Implementation

By Rajesh Vembu
•
started over 15 years ago

0 replies • 14257 views
Discussion

ecoAddRepeater - a long CPU time

Category: Digital Implementation

By Yemelya
•
updated over 15 years ago by Yemelya

3 replies • 2915 views
Discussion

Confliction in RTL power report using PSO method

Category: Digital Implementation

By tungthanhhoang
•
updated over 15 years ago by tungthanhhoang

2 replies • 15012 views
Discussion

Low-Power Tip of the Week: Placement of level shifter and isolation cells

Category: Digital Implementation

By archive
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updated over 15 years ago by navateja

1 replies • 24648 views
Discussion

Netlist with “assign” / RC and Encounter

Category: Digital Implementation

By Yemelya
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started over 15 years ago

0 replies • 14586 views
Discussion

Use of OA libs instead of lef file

Category: Digital Implementation

By bellekci
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started over 15 years ago

0 replies • 15121 views
Discussion

Verify placement of particular sub module (hierarchy) into dedicated area.

Category: Digital Implementation

By Yemelya
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updated over 15 years ago by Yemelya

2 replies • 14791 views
Discussion

EPS - rail analysis exits with VST-1048 error - CRITICAL

Category: Digital Implementation

By Vishnu Chada
•
started over 15 years ago

0 replies • 533 views
Discussion

How to implement dual threshold voltage in a circuit?

Category: Digital Implementation

By Preetisudha
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updated over 15 years ago by Dineshvv

2 replies • 16616 views
Discussion

DW components in Netlist Unresolved

Category: Digital Implementation

By suresh mandava
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updated over 15 years ago by suresh mandava

2 replies • 14941 views
Discussion

Re: how to do floorplanning for a flip chip

Category: Digital Implementation

By gops
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updated over 15 years ago by Kari

1 replies • 15330 views

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