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Digital Implementation

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  • Discussion

    Renaming a spare module

    Category: Digital Implementation

    By KVBABU KVBABU

    •

    updated over 14 years ago by Kari

    1 replies • 12829 views
  • Discussion

    clkgate setup timing violation is not treated by optDesign

    Category: Digital Implementation

    By greenblat greenblat

    •

    updated over 14 years ago by Kari

    3 replies • 13474 views
  • Discussion

    Encounter RTL-to-GDSII System 10.1 timing library include

    Category: Digital Implementation

    By vvijendr vvijendr

    •

    updated over 14 years ago by Kari

    1 replies • 12834 views
  • Discussion

    Current net list does not match wires file

    Category: Digital Implementation

    By raj7783 raj7783

    •

    updated over 14 years ago by raj7783

    1 replies • 12638 views
  • Discussion

    Encounter-verify geometry:SameNet violation

    Category: Digital Implementation

    By erin168 erin168

    •

    updated over 14 years ago by erin168

    1 replies • 1396 views
  • Discussion

    MMMC CTS

    Category: Digital Implementation

    By Rajesh Vembu Rajesh Vembu

    •

    started over 14 years ago

    0 replies • 12670 views
  • Discussion

    ecoAddRepeater - a long CPU time

    Category: Digital Implementation

    By Yemelya Yemelya

    •

    updated over 14 years ago by Yemelya

    3 replies • 2034 views
  • Discussion

    Confliction in RTL power report using PSO method

    Category: Digital Implementation

    By tungthanhhoang tungthanhhoang

    •

    updated over 14 years ago by tungthanhhoang

    2 replies • 13073 views
  • Discussion

    Low-Power Tip of the Week: Placement of level shifter and isolation cells

    Category: Digital Implementation

    By archive archive

    •

    updated over 14 years ago by navateja

    1 replies • 20553 views
  • Discussion

    Netlist with “assign” / RC and Encounter

    Category: Digital Implementation

    By Yemelya Yemelya

    •

    started over 14 years ago

    0 replies • 12981 views
  • Discussion

    Use of OA libs instead of lef file

    Category: Digital Implementation

    By bellekci bellekci

    •

    started over 14 years ago

    0 replies • 13377 views
  • Discussion

    Verify placement of particular sub module (hierarchy) into dedicated area.

    Category: Digital Implementation

    By Yemelya Yemelya

    •

    updated over 14 years ago by Yemelya

    2 replies • 12890 views
  • Discussion

    EPS - rail analysis exits with VST-1048 error - CRITICAL

    Category: Digital Implementation

    By Vishnu Chada Vishnu Chada

    •

    started over 14 years ago

    0 replies • 378 views
  • Discussion

    How to implement dual threshold voltage in a circuit?

    Category: Digital Implementation

    By Preetisudha Preetisudha

    •

    updated over 14 years ago by Dineshvv

    2 replies • 14250 views
  • Discussion

    DW components in Netlist Unresolved

    Category: Digital Implementation

    By suresh mandava suresh mandava

    •

    updated over 14 years ago by suresh mandava

    2 replies • 13065 views
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