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Digital Implementation

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  • Discussion

    optdesign deleting shielded nets

    Category: Digital Implementation

    By spach

    •

    started over 16 years ago

    0 replies • 14368 views
  • Discussion

    How to rename an instance?

    Category: Digital Implementation

    By jgentry

    •

    updated over 16 years ago by jgentry

    2 replies • 16062 views
  • Discussion

    eco route

    Category: Digital Implementation

    By spach

    •

    updated over 16 years ago by spach

    2 replies • 16292 views
  • Discussion

    negative delay backannotation

    Category: Digital Implementation

    By thescreen

    •

    updated over 16 years ago by thescreen

    1 replies • 21073 views
  • Discussion

    How to fix Noise bump violations in Encounter?

    Category: Digital Implementation

    By spach

    •

    updated over 16 years ago by BobD

    1 replies • 14843 views
  • Discussion

    CPF Functional simulation flow.

    Category: Digital Implementation

    By sandeepsuhas

    •

    updated over 16 years ago by sandeepsuhas

    1 replies • 14852 views
  • Discussion

    InsertRepeater violations

    Category: Digital Implementation

    By spach

    •

    updated over 16 years ago by PatBoug

    1 replies • 14724 views
  • Discussion

    Level Shifter Placement !

    Category: Digital Implementation

    By Ramya Deepika

    •

    updated over 16 years ago by Ramya Deepika

    1 replies • 16174 views
  • Discussion

    Which software to use?

    Category: Digital Implementation

    By theASICdude

    •

    updated over 16 years ago by archive

    2 replies • 14702 views
  • Discussion

    dbCommand needed for running a loop over different timing paths

    Category: Digital Implementation

    By 0007

    •

    updated over 16 years ago by BobD

    1 replies • 14495 views
  • Discussion

    all_fanin is returning a point when set to a variable

    Category: Digital Implementation

    By 0007

    •

    updated over 16 years ago by A Netherton

    6 replies • 18542 views
  • Discussion

    Configure Physical Hierarchy and Virtuoso Floorplanner

    Category: Digital Implementation

    By corpMule

    •

    started over 16 years ago

    0 replies • 14241 views
  • Discussion

    Transistor-Level STA solutions

    Category: Digital Implementation

    By Yemelya

    •

    started over 16 years ago

    0 replies • 14635 views
  • Discussion

    How to make SoC Encounter export Verilog with added VDD/VSS pins

    Category: Digital Implementation

    By LogicWizard

    •

    updated over 16 years ago by Vishnu Chada

    2 replies • 2365 views
  • Discussion

    Adding tie low cells on only requried pins

    Category: Digital Implementation

    By KVBABU

    •

    started over 16 years ago

    0 replies • 14513 views
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