Help needed in creating URM using SV

Hi Jalli.

You get these messages if you have not connected the SV interfaces correctly to your agent or DUT.
If for example you DUT has a port declared as an interface, it must be connected to an interface of the same type.

Without seeing your files it's hard to pinpoint the exact error, but I suggest you double check the connections from you top file going into the agent and DUT instances.

You can send me the files if you don't manage to resolve it : stephenh cadence.com

By the way, when you get an error message that you don't understand, try looking it up using the nchelp command. This usually gives some more details about the problem and how to solve it. For the two messages you described I pasted the nchelp commands and the output:

[sve/main] $ nchelp ncelab CUINMD
nchelp: 06.11-s003: (c) Copyright 1995-2007 Cadence Design Systems, Inc.
ncelab/CUINMD =
This is an incompatible connection. A Verilog interface must be connected
to a port of a Verilog instance. All other languages and connection
types are disallowed.

[sve/main] $ nchelp ncelab CUIMBC
nchelp: 06.11-s003: (c) Copyright 1995-2007 Cadence Design Systems, Inc.
ncelab/CUIMBC = An interface port declaration may not be left unconnected.
[sve/main] $


Sorry, the forum mashed my example. Here it is again:

$ nchelp ncelab CUINMD
nchelp: 06.11-s003: (c) Copyright 1995-2007 Cadence Design Systems, Inc.
ncelab/CUINMD =
        This is an incompatible connection.  A Verilog interface must be connected
        to a port of a Verilog instance.  All other languages and connection
        types are disallowed.
$ nchelp ncelab CUIMBC
nchelp: 06.11-s003: (c) Copyright 1995-2007 Cadence Design Systems, Inc.
ncelab/CUIMBC =
        An interface port declaration may not be left unconnected.

Hi Steve!,
Thanks a lot for your instant reply!!!!!
I've seen your reply and I've sent the code to your mailID..i.e., "stephenh@cadence.com"
I've corrected all the possiblities you've mentioned and also I use nchelp frequently for any error I get but for this problem I couldn't get the solution.....so plz help me in this regards. Please do letme know whether your mailID is proper or not as mentioned here.

Thanks in advance,
Regards,
Jalli

The port connection to the UVC includes the dut_if. Therefore, make sure you have a top level that instantiates the dut_if and then connects it to the port of the UVC.

Example:

module top;

ahb_interface dut_if (); // must instantiate interface

ahb_uvc env (dut_if); // and connect it to module with interface port

endmodule

module ahb_uvc (interface dut_if);
...
endmodule


Tim

Hi Jally.

I just replied to your mail with some more info. For the record, because you have only compiled the agent, and no env or testbench to instantiate the agent, the agent's interface is left unconnected, which is illegal in SystemVerilog.

You should refer to the URM docs, and also the vr_xbus example that comes wit IPCM.
You can find the vr_xbus example files under the IPCM installation, like this:
  IPCM/6.11/ipcm/urm_lib/sv_mb_ex_lib/vr_xbus

Normally your testbench hierarchy would look something like this:

sve   (top module)
 |- dut_if   (instance of dut interface)
 |- dut_wrapper  (instance)
 |     |- dut   (the real dut)
 |- sips_ahb_env  (instance of the AHB env)
 |    |- sips_ahb_master_agent
 |    |    |- sips_ahb_master_monitor
 |    |    |- sips_ahb_master_driver
 |    |    |- sips_ahb_master_bfm
 |    |- sips_ahb_slave_agent
 |    |    |- (structure as per master agent)
 |- any_other_interface_env
      |- any_other_interface_master_agent
      |     |- any_other_interface_master_monitor
      |     |- ...
      |- any_other_interface_slave_agent
 

Hi Steve,

Thanks once again!....I'll rectify my code and let you know very soon about it!

Regards,
Jalli

Hi Steve,

It worked out after I created any_other_env.sv and any_other_tb_top.sv......Error gone!

Regards,
Jalli

Hi Jalli.

Glad to hear you fixed the problem :-)

We always recommend that you build the whole URM structure (env, master and slave agents).
If you do this, it has several advantages, including:
1) Consistent structure, so your code is more understandable.
2) You can develop the protocol without needing a real DUT (master agent talks to slave agent for verif env bring-up).
3) You can use the inactive part (e.g. slave agent) as a passive monitor of your DUT.
This is most helpful when you have multiple slaves and you want coverage or checking on each slave DUT.

There's loads more reasons, but those are a good start :)

Hi Steve,

Ok....I'll do accordingly....right now I'm concentrating on writing the code for slave agent!
Thanks a lot for your suggestions and guidance!....I'll follow accordingly and will definetly seek your help if I get struck somewhere!

Regards,
Jalli

Hello Steve,

My environment is up but I've a warning based on system task which is shown as below:

vb = $urm_get_message_verbosity(module_path);
|
ncelab: *W,MISSYST (./examples/urm_util_pkg.sv,263|32): Unrecognized system task or function (did not match built-in or user-defined names) [2.7.4(IEEE Std 1364-2001)].
if ($urm_is_severity_defined())
|
ncelab: *W,MISSYST (./examples/urm_util_pkg.sv,458|30): Unrecognized system task or function (did not match built-in or user-defined names) [2.7.4(IEEE Std 1364-2001)].
sv = $urm_get_check_severity(module_path);
|
ncelab: *W,MISSYST (./examples/urm_util_pkg.sv,464|29): Unrecognized system task or function (did not match built-in or user-defined names) [2.7.4(IEEE Std 1364-2001)].

Can you please tell me in which system file these tasks are included so that I can remove these warnings by including those files!!?

Thanks a lot in advance!,
Jalli