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Functional Verification

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    Can I force or probe a signal in vhdl module from verilog top testbench?

    Category: Functional Verification

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    updated over 18 years ago by archive

    6 replies • 17243 views
  • Discussion

    How to tackle 'Aborted' properties.

    Category: Functional Verification

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    updated over 18 years ago by archive

    3 replies • 6104 views
  • Discussion

    How frequently should Transactor work?

    Category: Functional Verification

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    updated over 18 years ago by archive

    1 replies • 13245 views
  • Discussion

    Internal IUS error

    Category: Functional Verification

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    updated over 18 years ago by archive

    7 replies • 16342 views
  • Discussion

    How to probe and view the variable wave in class?

    Category: Functional Verification

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    updated over 18 years ago by archive

    3 replies • 19727 views
  • Discussion

    parsing the arguments from command line

    Category: Functional Verification

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    updated over 18 years ago by archive

    3 replies • 19693 views
  • Discussion

    Come see the URM in action on May 2

    Category: Functional Verification

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    started over 18 years ago

    0 replies • 12519 views
  • Discussion

    Passing e defines through Model Sim

    Category: Functional Verification

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    updated over 18 years ago by archive

    2 replies • 13606 views
  • Discussion

    About URM library

    Category: Functional Verification

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    updated over 18 years ago by archive

    2 replies • 13275 views
  • Discussion

    C++ code through DPI?

    Category: Functional Verification

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    updated over 18 years ago by archive

    2 replies • 15245 views
  • Discussion

    SC-SV-Verilog interface

    Category: Functional Verification

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    started over 18 years ago

    0 replies • 12620 views
  • Discussion

    SC and SV co-simulation in IUS?

    Category: Functional Verification

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    updated over 18 years ago by archive

    3 replies • 13960 views
  • Discussion

    Reg : problem with reg declaration in IUS58

    Category: Functional Verification

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    updated over 18 years ago by archive

    4 replies • 14019 views
  • Discussion

    printf in IUS6.01

    Category: Functional Verification

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    updated over 18 years ago by archive

    6 replies • 15110 views
  • Discussion

    forall and endpoint/ended

    Category: Functional Verification

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    updated over 18 years ago by archive

    1 replies • 974 views
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