Functional Verification

Latest Posts

Discussion

[help]ies and ius

Category: Functional Verification

By tonychain

$usertype
•
started over 14 years ago

0 replies • 624 views
Discussion

behavior of disabling constraint_mode from subclass

Category: Functional Verification

By xbluewings

$usertype
•
started over 14 years ago

0 replies • 13273 views
Discussion

can custom bidirectional data-types in systemverilog package be used in vhdl entity port declarations.

Category: Functional Verification

By skillseeker

$usertype
•
started over 14 years ago

0 replies • 13591 views
Discussion

How to connect systemC timed model to OVM environment

Category: Functional Verification

By viraj shah

$usertype
•
updated over 14 years ago by Adam Sherer

4 replies • 15839 views
Discussion

Seek help to download VTP_TestBuilder_01.30_s008.tar

Category: Functional Verification

By WorldMaker

$usertype
•
updated over 14 years ago by tpylant

1 replies • 13906 views
Discussion

Simple UVM Bench Issue

Category: Functional Verification

By ashfaqh

$usertype
•
updated over 14 years ago by ashfaqh

1 replies • 14311 views
Discussion

Simple UVM Bench Issue

Category: Functional Verification

By ashfaqh

$usertype
•
started over 14 years ago

0 replies • 13350 views
Discussion

problems running NCISM in batch mode

Category: Functional Verification

By gperry

$usertype
•
started over 14 years ago

0 replies • 13864 views
Discussion

Gate level Simulation

Category: Functional Verification

By Mandate

$usertype
•
updated over 14 years ago by tpylant

4 replies • 17323 views
Discussion

how to Enable/disable covergroups with in classes

Category: Functional Verification

By SACHPAT

$usertype
•
started over 14 years ago

0 replies • 2357 views
Discussion

Gate Level Simulation

Category: Functional Verification

By Mandate

$usertype
•
started over 14 years ago

0 replies • 13723 views
Discussion

Passing a timing file in ncsim instead of ncelab

Category: Functional Verification

By mcheah

$usertype
•
started over 14 years ago

0 replies • 14683 views
Discussion

Stretching data during 2 clock cycle

Category: Functional Verification

By gilazilla

$usertype
•
started over 14 years ago

0 replies • 13651 views
Discussion

How to short the time during ncelab when do gate level simulation

Category: Functional Verification

By zlzg12345

$usertype
•
updated over 14 years ago by tpylant

1 replies • 13928 views
Discussion

Assertions

Category: Functional Verification

By livid

$usertype
•
updated over 14 years ago by srinicvc

2 replies • 14544 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.