Functional Verification

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Discussion

randomizing real values in vsif

Category: Functional Verification

By Petros

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updated over 3 years ago by Petros

4 replies • 10641 views
Discussion

How to avoid the rounded variable in simulation?

Category: Functional Verification

By Makka Pakka

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started over 3 years ago

0 replies • 8546 views
Discussion

[Xcelium] How to re-compile the design+testbench from GUI?

Category: Functional Verification

By amnldm

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updated over 3 years ago by StephenH

1 replies • 5517 views
Discussion

How to add regression coverage to another in vManager?

Category: Functional Verification

By ArielElia95

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updated over 3 years ago by ArielElia95

4 replies • 13345 views
Discussion

Using vManager to see coverage in the same way ximc does

Category: Functional Verification

By ArielElia95

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updated over 3 years ago by StephenH

1 replies • 11635 views
Discussion

DRM job removed. Job 2751721[3] removed by DRM. DRM Job status: TERMINATED Debug aids: Job output:

Category: Functional Verification

By Rolly

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started over 3 years ago

0 replies • 1126 views
Discussion

Xcelium PCIONC error on parameterized harness inout

Category: Functional Verification

By bdiz

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updated over 3 years ago by bdiz

2 replies • 15721 views
Discussion

"Direction" of EEnet connection points?

Category: Functional Verification

By DanHerbison

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updated over 3 years ago by drdanmc

1 replies • 2574 views
Discussion

Significance of virtual reset and port association with reset

Category: Functional Verification

By Advait

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started over 3 years ago

0 replies • 9426 views
Discussion

Different result with vmanager and standalone simulation, with same seed

Category: Functional Verification

By djdjuric

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updated over 3 years ago by StephenH

7 replies • 14447 views
Discussion

Indago waveform is not showing after Design reload

Category: Functional Verification

By Abhishek Jaiswal

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updated over 3 years ago by dfhe

1 replies • 11414 views
Discussion

xrun cannot initialize values

Category: Functional Verification

By quantumion

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updated over 3 years ago by Hugdfig

3 replies • 14096 views
Discussion

error happen when using Debugging UVM with simvision

Category: Functional Verification

By galenxiao

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updated over 3 years ago by galenxiao

2 replies • 12616 views
Discussion

different results from formal verification and simulation

Category: Functional Verification

By anshchawla

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updated over 3 years ago by anshchawla

1 replies • 10979 views
Discussion

report unused verilog packages

Category: Functional Verification

By Max Bjurling

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updated over 3 years ago by Max Bjurling

4 replies • 13499 views

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