Functional Verification

Latest Posts

Discussion

Getting ERROR when I try to save and restore waveform.

Category: Functional Verification

By Gopi R

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started over 10 years ago

0 replies • 13437 views
Discussion

Getting SWIFT internal error:bad call of realloc:Failed to allocate block

Category: Functional Verification

By usha sudhagar

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started over 10 years ago

0 replies • 542 views
Discussion

Help with Optimizer (model parameters)

Category: Functional Verification

By CarloDeSanti

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started over 10 years ago

0 replies • 13320 views
Discussion

Spice Model for VPWL_F_RE_FOREVER

Category: Functional Verification

By Nikesh Bansal

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updated over 10 years ago by Nikesh Bansal

2 replies • 14294 views
Discussion

How to probe VHDL function variables in ncsim?

Category: Functional Verification

By venkub

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updated over 10 years ago by David Rogoff

3 replies • 17728 views
Discussion

Facing issue while running ncelab step after ncverilog

Category: Functional Verification

By Tanvinxp

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updated over 10 years ago by StephenH

1 replies • 17711 views
Discussion

merging code coverage with different .ccf

Category: Functional Verification

By marsun

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started over 10 years ago

0 replies • 14165 views
Discussion

failed to generate .saif using "irun" command -> "Unrecognized system task or function"

Category: Functional Verification

By childs

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started over 10 years ago

0 replies • 1263 views
Discussion

set/reset inversion

Category: Functional Verification

By AmbroseLau

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started over 10 years ago

0 replies • 440 views
Discussion

About timing precision of sdf file simulated in ncsim

Category: Functional Verification

By daxingxing

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updated over 10 years ago by daxingxing

2 replies • 17144 views
Discussion

Merge conflict with iccr

Category: Functional Verification

By Vict2

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updated over 10 years ago by Vict2

6 replies • 15873 views
Discussion

How to exclude a register or bit in IMC by certain value

Category: Functional Verification

By brucelu104

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started over 10 years ago

0 replies • 14540 views
Discussion

Connecting VHDL port to system verilog interface definition in UVM

Category: Functional Verification

By sunil kr

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updated over 11 years ago by StephenH

4 replies • 16746 views
Discussion

NCVHDL simulation error

Category: Functional Verification

By Jinesh K B

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updated over 11 years ago by Jinesh K B

2 replies • 14275 views
Discussion

ncsim: *E,DENOTS: No time specification given for value: after

Category: Functional Verification

By binm

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started over 11 years ago

0 replies • 873 views

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