Logic Design

Latest Posts

Discussion

Difference Between PLE, Spatial, Physical

Category: Logic Design

By sureshm

$usertype
•
updated over 13 years ago by grasshopper

1 replies • 19578 views
Discussion

Any comments on the RC Physical Timing co-relation with EDI?

Category: Logic Design

By sureshm

$usertype
•
updated over 13 years ago by grasshopper

1 replies • 13939 views
Discussion

Simulating verilog using cadence

Category: Logic Design

By MTP3

$usertype
•
updated over 13 years ago by MTP3

1 replies • 14239 views
Discussion

Regarding retiming....which license is required

Category: Logic Design

By ChInNi miSSing

$usertype
•
updated over 13 years ago by mclarke

1 replies • 13937 views
Discussion

Check out Conformal documentation via its web interface!

Category: Logic Design

By hummingbird

$usertype
•
updated over 13 years ago by tstark

1 replies • 14535 views
Discussion

Why boundary_opto cause to LEC fail?

Category: Logic Design

By PengpengHao

$usertype
•
updated over 13 years ago by tstark

1 replies • 14140 views
Discussion

Propagate a clock from .LIB of a block

Category: Logic Design

By randomax

$usertype
•
started over 13 years ago

0 replies • 13783 views
Discussion

How to synthesize without scan cell replacement

Category: Logic Design

By Maso

$usertype
•
updated over 13 years ago by Maso

7 replies • 23161 views
Discussion

Checking equivalence of buffer trees

Category: Logic Design

By BufferTree

$usertype
•
updated over 13 years ago by tstark

1 replies • 14893 views
Discussion

How to calculate speed for each path_group in RTL Compiler

Category: Logic Design

By Maso

$usertype
•
updated over 13 years ago by Maso

2 replies • 14177 views
Discussion

How can I remove module before writing whole netlist out

Category: Logic Design

By Maso

$usertype
•
updated over 13 years ago by Maso

2 replies • 14654 views
Discussion

Cadence encounter(9.x) crashes while doing "verify_geometries"

Category: Logic Design

By Akatyal22

$usertype
•
started over 13 years ago

0 replies • 368 views
Discussion

Do you have issues using multibit flops

Category: Logic Design

By AntonioL

$usertype
•
updated over 13 years ago by tstark

1 replies • 15870 views
Discussion

Hello. How to add a custom cell to the freePDK45nm standard cell library.

Category: Logic Design

By Thommandram

$usertype
•
updated over 13 years ago by mcaruso

1 replies • 13996 views
Discussion

Conformal ECO Flow Basic Question

Category: Logic Design

By moogyd

$usertype
•
updated over 13 years ago by hummingbird

1 replies • 16410 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.