Logic Design

Latest Posts

Discussion

Error in Cadence RTL Compiler when estimating Power using VCD

Category: Logic Design

By shaunisu
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started over 6 years ago

0 replies • 13918 views
Discussion

for choosing the frequency range of any digital circuit

Category: Logic Design

By jayakandpal
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started over 6 years ago

0 replies • 12786 views
Discussion

RTL compiler crash

Category: Logic Design

By shaunisu
•
started over 6 years ago

0 replies • 13665 views
Discussion

What does area reported by RTL compiler mean?

Category: Logic Design

By rexnyu
•
updated over 6 years ago by Andrew Beckett

6 replies • 32503 views
Discussion

Differences between "report power" and "report scan_power"

Category: Logic Design

By nokta
•
started over 6 years ago

0 replies • 1510 views
Discussion

Irun driver contention with SystemVerilog port defaults (15.20.001)

Category: Logic Design

By Palaparthy
•
started over 7 years ago

0 replies • 13329 views
Discussion

RC compiler and ports consisting of arrays of vectors

Category: Logic Design

By MarkusK
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updated over 7 years ago by MarkusK

2 replies • 14019 views
Discussion

port array synthesis

Category: Logic Design

By olalivier
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started over 7 years ago

0 replies • 14701 views
Discussion

Genus UI - How to set attribute?

Category: Logic Design

By mbrandalero
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started over 7 years ago

0 replies • 5946 views
Discussion

Genus : Auto_ungroup breaks functionality

Category: Logic Design

By Schriek
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started over 7 years ago

0 replies • 14184 views
Discussion

Problems with simulating counter chips

Category: Logic Design

By zfan
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started over 7 years ago

0 replies • 13092 views
Discussion

Is there a way to set the `default_nettype directive through the command-line when running irun?

Category: Logic Design

By crclayton
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started over 7 years ago

0 replies • 14133 views
Discussion

Genus Synthesis - Cost Groups

Category: Logic Design

By Heaton15
•
started over 7 years ago

0 replies • 3650 views
Discussion

Delay in Or cad pspice

Category: Logic Design

By amrita1503
•
updated over 7 years ago by amrita1503

2 replies • 14668 views
Discussion

Hierarchical design component used report

Category: Logic Design

By chillman
•
started over 7 years ago

0 replies • 12829 views

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