Logic Design

Latest Posts

Discussion

Difference Between PLE, Spatial, Physical

Category: Logic Design

By sureshm
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updated over 13 years ago by grasshopper

1 replies • 18401 views
Discussion

Any comments on the RC Physical Timing co-relation with EDI?

Category: Logic Design

By sureshm
•
updated over 13 years ago by grasshopper

1 replies • 13149 views
Discussion

Simulating verilog using cadence

Category: Logic Design

By MTP3
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updated over 13 years ago by MTP3

1 replies • 13412 views
Discussion

Regarding retiming....which license is required

Category: Logic Design

By ChInNi miSSing
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updated over 13 years ago by mclarke

1 replies • 13117 views
Discussion

Check out Conformal documentation via its web interface!

Category: Logic Design

By hummingbird
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updated over 13 years ago by tstark

1 replies • 13729 views
Discussion

Why boundary_opto cause to LEC fail?

Category: Logic Design

By PengpengHao
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updated over 13 years ago by tstark

1 replies • 13339 views
Discussion

Propagate a clock from .LIB of a block

Category: Logic Design

By randomax
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started over 13 years ago

0 replies • 13061 views
Discussion

How to synthesize without scan cell replacement

Category: Logic Design

By Maso
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updated over 13 years ago by Maso

7 replies • 21323 views
Discussion

Checking equivalence of buffer trees

Category: Logic Design

By BufferTree
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updated over 13 years ago by tstark

1 replies • 13928 views
Discussion

How to calculate speed for each path_group in RTL Compiler

Category: Logic Design

By Maso
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updated over 13 years ago by Maso

2 replies • 13334 views
Discussion

How can I remove module before writing whole netlist out

Category: Logic Design

By Maso
•
updated over 13 years ago by Maso

2 replies • 13736 views
Discussion

Cadence encounter(9.x) crashes while doing "verify_geometries"

Category: Logic Design

By Akatyal22
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started over 13 years ago

0 replies • 335 views
Discussion

Do you have issues using multibit flops

Category: Logic Design

By AntonioL
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updated over 13 years ago by tstark

1 replies • 14851 views
Discussion

Hello. How to add a custom cell to the freePDK45nm standard cell library.

Category: Logic Design

By Thommandram
•
updated over 13 years ago by mcaruso

1 replies • 13186 views
Discussion

Conformal ECO Flow Basic Question

Category: Logic Design

By moogyd
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updated over 13 years ago by hummingbird

1 replies • 15380 views

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