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Mixed-Signal Design

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  • Discussion

    Verilog-A to access wire bus of DUT

    Category: Mixed-Signal Design

    By slim15 slim15

    •

    updated over 7 years ago by Dimitra Papazoglou

    1 replies • 17582 views
  • Discussion

    ModGen and Common Centroid Layout

    Category: Mixed-Signal Design

    By growingmind growingmind

    •

    updated over 7 years ago by Dimitra Papazoglou

    1 replies • 17217 views
  • Discussion

    Getting Started with Verilog-A, Verilog-AMS SImulation in Cadence

    Category: Mixed-Signal Design

    By growingmind growingmind

    •

    updated over 7 years ago by Andrew Beckett

    3 replies • 33801 views
  • Discussion

    Difference between bmslib and ahdlib in Cadence

    Category: Mixed-Signal Design

    By growingmind growingmind

    •

    updated over 7 years ago by Andrew Beckett

    1 replies • 17428 views
  • Discussion

    best resources and RAKs on Verilog A, Verilog AMS and AMS designer, ADE assembler test/verification and SimVision

    Category: Mixed-Signal Design

    By mhkvy4 mhkvy4

    •

    updated over 7 years ago by Andrew Beckett

    3 replies • 2226 views
  • Discussion

    how to measure corner frquency in verilogA

    Category: Mixed-Signal Design

    By vamshiky vamshiky

    •

    updated over 7 years ago by Andrew Beckett

    5 replies • 14316 views
  • Discussion

    question on acmatch sim in spectre

    Category: Mixed-Signal Design

    By vamshiky vamshiky

    •

    updated over 7 years ago by vamshiky

    2 replies • 13715 views
  • Discussion

    unable to simulate this veriloga code in cadence

    Category: Mixed-Signal Design

    By noob1 noob1

    •

    updated over 7 years ago by noob1

    2 replies • 14084 views
  • Discussion

    eye diagram problem

    Category: Mixed-Signal Design

    By ManuelSuarez ManuelSuarez

    •

    updated over 7 years ago by ManuelSuarez

    2 replies • 15461 views
  • Discussion

    Automate creation of pins in a top level layout directly above sub-cell pins

    Category: Mixed-Signal Design

    By JWHoll JWHoll

    •

    updated over 7 years ago by Andrew Beckett

    1 replies • 14314 views
  • Discussion

    Statistical Contribution or criticality of each device

    Category: Mixed-Signal Design

    By Charanraj Mohan Charanraj Mohan

    •

    updated over 7 years ago by Charanraj Mohan

    2 replies • 14188 views
  • Discussion

    controlling mismatch & other related queries.

    Category: Mixed-Signal Design

    By Charanraj Mohan Charanraj Mohan

    •

    updated over 7 years ago by Charanraj Mohan

    2 replies • 2525 views
  • Discussion

    VCD FIle Input to ADE-L

    Category: Mixed-Signal Design

    By abalbason abalbason

    •

    updated over 7 years ago by Andrew Beckett

    3 replies • 20726 views
  • Discussion

    How to follow a wire in the layout?

    Category: Mixed-Signal Design

    By MohsenShah MohsenShah

    •

    updated over 7 years ago by MohsenShah

    2 replies • 14171 views
  • Discussion

    ADEL - spectre , DC analysis writefinal param is ignored

    Category: Mixed-Signal Design

    By marcelpreda marcelpreda

    •

    updated over 7 years ago by marcelpreda

    2 replies • 2001 views
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