Mixed-Signal Design

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Discussion

ncelab: *F,OSDINF: instance 'ABC@XYZ .I27' of design unit 'S2LINVV1D0H' is a leaf instance and is unresolved

Category: Mixed-Signal Design

By Nicolas Callens
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started over 6 years ago

0 replies • 3635 views
Discussion

GMRES solver could not converge to the desired tolerance. Please try to increase krylov_size Error while running Pnoise

Category: Mixed-Signal Design

By Munish86
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updated over 6 years ago by Munish86

4 replies • 16919 views
Discussion

Supply sensitive connect modules vs Dynamic connect modules

Category: Mixed-Signal Design

By sansh
•
started over 6 years ago

0 replies • 14356 views
Discussion

how to add Verilog testbench for AMS simulation

Category: Mixed-Signal Design

By ntuzxy
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updated over 6 years ago by riahm

2 replies • 18183 views
Discussion

AMS simulation error reporting

Category: Mixed-Signal Design

By lanlin
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updated over 6 years ago by lanlin

8 replies • 18532 views
Discussion

I want to import with verilog in virtuoso(icfb)

Category: Mixed-Signal Design

By JOILEB
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updated over 6 years ago by Andrew Beckett

5 replies • 4185 views
Discussion

The veriloga code when simulted in cadence shows the following error though all the syntax and identifiers match the accellera. Thanks in advance.

Category: Mixed-Signal Design

By Avieee
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updated over 6 years ago by Avieee

4 replies • 14799 views
Discussion

Weird voltage level in verilogA simulation

Category: Mixed-Signal Design

By hafiz2431
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updated over 6 years ago by silviabarnett

2 replies • 13775 views
Discussion

Missing EEnet connect modules

Category: Mixed-Signal Design

By drdanmc
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updated over 6 years ago by Frank Wiedmann

6 replies • 20090 views
Discussion

How to use AMS design flow with standard cell library?

Category: Mixed-Signal Design

By dogrush
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updated over 6 years ago by BijoyKundu

4 replies • 56263 views
Discussion

Simulation of simple Verilog-AMS testbench failed

Category: Mixed-Signal Design

By pyohayo
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updated over 6 years ago by Andrew Beckett

2 replies • 14433 views
Discussion

Simulating CDL netlist in AMS UNL

Category: Mixed-Signal Design

By mayaAMS
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started over 6 years ago

0 replies • 13747 views
Discussion

Plotting a digital bus as an analog signal

Category: Mixed-Signal Design

By mwb1
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updated over 6 years ago by Andrew Beckett

3 replies • 24123 views
Discussion

I/O libraries required from Cadence?

Category: Mixed-Signal Design

By mohammadalizia
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updated over 6 years ago by Andrew Beckett

1 replies • 1029 views
Discussion

Inbuilt math functions for RNM SV modelling of mixed signal blocks

Category: Mixed-Signal Design

By Shanto
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started over 6 years ago

0 replies • 12843 views

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