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Mixed-Signal Design

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  • Discussion

    Import Wavescan waveform (Spectre) in SimVision

    Category: Mixed-Signal Design

    By pyohayo

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    updated over 6 years ago by pyohayo

    6 replies • 19280 views
  • Discussion

    Format of "VCD Info File"

    Category: Mixed-Signal Design

    By pyohayo

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    updated over 6 years ago by pyohayo

    16 replies • 30949 views
  • Discussion

    Virtuoso not plotting digital signals in AMS simulation

    Category: Mixed-Signal Design

    By riahm

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    started over 6 years ago

    0 replies • 14465 views
  • Discussion

    AMS simulation with digital simulator on top

    Category: Mixed-Signal Design

    By pvuc

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    updated over 6 years ago by pvuc

    2 replies • 15946 views
  • Discussion

    PAM4 Signal using ahdllib or bmslib

    Category: Mixed-Signal Design

    By growingmind

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    updated over 6 years ago by Andrew Beckett

    3 replies • 18581 views
  • Discussion

    Using AMS simulation final values as stimulus for RF circuit

    Category: Mixed-Signal Design

    By jslaton

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    started over 6 years ago

    0 replies • 13489 views
  • Discussion

    Virtuoso ADEXL cluster(SGE) simulation

    Category: Mixed-Signal Design

    By riahm

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    updated over 6 years ago by riahm

    2 replies • 2574 views
  • Discussion

    VHDL view to use in heirarchy editor

    Category: Mixed-Signal Design

    By riahm

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    updated over 6 years ago by riahm

    8 replies • 23833 views
  • Discussion

    ncelab: *F,OSDINF: instance 'ABC@XYZ .I27' of design unit 'S2LINVV1D0H' is a leaf instance and is unresolved

    Category: Mixed-Signal Design

    By Nicolas Callens

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    started over 6 years ago

    0 replies • 3830 views
  • Discussion

    GMRES solver could not converge to the desired tolerance. Please try to increase krylov_size Error while running Pnoise

    Category: Mixed-Signal Design

    By Munish86

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    updated over 6 years ago by Munish86

    4 replies • 17991 views
  • Discussion

    Supply sensitive connect modules vs Dynamic connect modules

    Category: Mixed-Signal Design

    By sansh

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    started over 6 years ago

    0 replies • 15107 views
  • Discussion

    how to add Verilog testbench for AMS simulation

    Category: Mixed-Signal Design

    By ntuzxy

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    updated over 6 years ago by riahm

    2 replies • 19434 views
  • Discussion

    AMS simulation error reporting

    Category: Mixed-Signal Design

    By lanlin

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    updated over 6 years ago by lanlin

    8 replies • 19687 views
  • Discussion

    I want to import with verilog in virtuoso(icfb)

    Category: Mixed-Signal Design

    By JOILEB

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    updated over 6 years ago by Andrew Beckett

    5 replies • 4842 views
  • Discussion

    The veriloga code when simulted in cadence shows the following error though all the syntax and identifiers match the accellera. Thanks in advance.

    Category: Mixed-Signal Design

    By Avieee

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    updated over 6 years ago by Avieee

    4 replies • 15769 views
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