Mixed-Signal Design

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Discussion

userdata file in Liberate

Category: Mixed-Signal Design

By anandmohan

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updated over 7 years ago by anandmohan

1 replies • 14135 views
Discussion

Doubt reg a .lib file parameter

Category: Mixed-Signal Design

By anandmohan

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updated over 7 years ago by Guangjun Cao

3 replies • 15652 views
Discussion

Error in Liberate on parsing extracted netlist

Category: Mixed-Signal Design

By anandmohan

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started over 7 years ago

0 replies • 13434 views
Discussion

Error running Liberate_AMS

Category: Mixed-Signal Design

By anandmohan

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updated over 7 years ago by anandmohan

2 replies • 14130 views
Discussion

Not fitting lmax-lmin, wmax-wmin or areamax-areamin range

Category: Mixed-Signal Design

By Nicolas Callens

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updated over 7 years ago by Nicolas Callens

4 replies • 22273 views
Discussion

Liberate_AMS for .lib generation.

Category: Mixed-Signal Design

By anandmohan

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updated over 7 years ago by anandmohan

17 replies • 23489 views
Discussion

spectre solver for veriloga

Category: Mixed-Signal Design

By Yuanqi

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updated over 7 years ago by Andrew Beckett

7 replies • 17472 views
Discussion

irun is not recognizing .scs files

Category: Mixed-Signal Design

By 0nTheG0

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updated over 7 years ago by 0nTheG0

2 replies • 15292 views
Discussion

Verilog-A to access wire bus of DUT

Category: Mixed-Signal Design

By slim15

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updated over 7 years ago by Dimitra Papazoglou

1 replies • 18492 views
Discussion

ModGen and Common Centroid Layout

Category: Mixed-Signal Design

By growingmind

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updated over 7 years ago by Dimitra Papazoglou

1 replies • 18281 views
Discussion

Getting Started with Verilog-A, Verilog-AMS SImulation in Cadence

Category: Mixed-Signal Design

By growingmind

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updated over 7 years ago by Andrew Beckett

3 replies • 35561 views
Discussion

Difference between bmslib and ahdlib in Cadence

Category: Mixed-Signal Design

By growingmind

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updated over 7 years ago by Andrew Beckett

1 replies • 18419 views
Discussion

best resources and RAKs on Verilog A, Verilog AMS and AMS designer, ADE assembler test/verification and SimVision

Category: Mixed-Signal Design

By mhkvy4

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updated over 7 years ago by Andrew Beckett

3 replies • 2552 views
Discussion

how to measure corner frquency in verilogA

Category: Mixed-Signal Design

By vamshiky

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updated over 7 years ago by Andrew Beckett

5 replies • 15258 views
Discussion

question on acmatch sim in spectre

Category: Mixed-Signal Design

By vamshiky

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updated over 7 years ago by vamshiky

2 replies • 14486 views

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