Mixed-Signal Design

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Discussion

Fmax setting in nport cell of analogLib

Category: Mixed-Signal Design

By akshay91

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updated over 7 years ago by Andrew Beckett

3 replies • 16316 views
Discussion

Schematic Extraction of Standard Cells of TSMC 40nm and AMS

Category: Mixed-Signal Design

By anurans

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updated over 7 years ago by Saloni Chhabra

1 replies • 16090 views
Discussion

how to convert text string to integer in VerilogA?

Category: Mixed-Signal Design

By DavidLou

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updated over 7 years ago by DavidLou

12 replies • 25769 views
Discussion

possible to instantiate Verilog module in VerilogA?

Category: Mixed-Signal Design

By DavidLou

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updated over 7 years ago by DavidLou

6 replies • 20891 views
Discussion

Generating a spectre netlist(.scs) with a corner conditions in command line

Category: Mixed-Signal Design

By rotanudad

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updated over 7 years ago by Andrew Beckett

1 replies • 15137 views
Discussion

Waveform Viewer selection in AMS Designer

Category: Mixed-Signal Design

By DavidLou

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updated over 7 years ago by DavidLou

10 replies • 22755 views
Discussion

userdata file in Liberate

Category: Mixed-Signal Design

By anandmohan

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updated over 7 years ago by anandmohan

1 replies • 14596 views
Discussion

Doubt reg a .lib file parameter

Category: Mixed-Signal Design

By anandmohan

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updated over 7 years ago by Guangjun Cao

3 replies • 16151 views
Discussion

Error in Liberate on parsing extracted netlist

Category: Mixed-Signal Design

By anandmohan

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started over 7 years ago

0 replies • 13835 views
Discussion

Error running Liberate_AMS

Category: Mixed-Signal Design

By anandmohan

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updated over 7 years ago by anandmohan

2 replies • 14588 views
Discussion

Not fitting lmax-lmin, wmax-wmin or areamax-areamin range

Category: Mixed-Signal Design

By Nicolas Callens

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updated over 7 years ago by Nicolas Callens

4 replies • 22951 views
Discussion

Liberate_AMS for .lib generation.

Category: Mixed-Signal Design

By anandmohan

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updated over 7 years ago by anandmohan

17 replies • 24455 views
Discussion

spectre solver for veriloga

Category: Mixed-Signal Design

By Yuanqi

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updated over 7 years ago by Andrew Beckett

7 replies • 18210 views
Discussion

irun is not recognizing .scs files

Category: Mixed-Signal Design

By 0nTheG0

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updated over 7 years ago by 0nTheG0

2 replies • 15805 views
Discussion

Verilog-A to access wire bus of DUT

Category: Mixed-Signal Design

By slim15

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updated over 7 years ago by Dimitra Papazoglou

1 replies • 19015 views

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