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Mixed-Signal Design

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  • Discussion

    SPICE built in primitives in an AMS simulation

    Category: Mixed-Signal Design

    By mhkvy4

    •

    updated over 8 years ago by Andrew Beckett

    9 replies • 21969 views
  • Discussion

    Rapid Adoption Kit (RAK) for AMS Designer

    Category: Mixed-Signal Design

    By anmos

    •

    updated over 8 years ago by Frank Wiedmann

    1 replies • 17963 views
  • Discussion

    Simulating *.vams generated from ADE-L in DoT flow

    Category: Mixed-Signal Design

    By aarthymani

    •

    updated over 8 years ago by aarthymani

    4 replies • 17797 views
  • Discussion

    Vector net cannot be connected to a Spice/Spectre instance by port name.

    Category: Mixed-Signal Design

    By FormerMember

    •

    updated over 8 years ago by Andrew Beckett

    7 replies • 9135 views
  • Discussion

    table_model multi-column data file

    Category: Mixed-Signal Design

    By olalivier

    •

    updated over 8 years ago by Andrew Beckett

    3 replies • 19357 views
  • Discussion

    LC VCO startup issue for different transient algorithms

    Category: Mixed-Signal Design

    By Cherag

    •

    updated over 8 years ago by Cherag

    2 replies • 18082 views
  • Discussion

    import spice model to one of the commercial OTA ICS

    Category: Mixed-Signal Design

    By nahlaelazab

    •

    updated over 8 years ago by Andrew Beckett

    1 replies • 16840 views
  • Discussion

    Fmax setting in nport cell of analogLib

    Category: Mixed-Signal Design

    By akshay91

    •

    updated over 8 years ago by Andrew Beckett

    3 replies • 17300 views
  • Discussion

    Schematic Extraction of Standard Cells of TSMC 40nm and AMS

    Category: Mixed-Signal Design

    By anurans

    •

    updated over 8 years ago by Saloni Chhabra

    1 replies • 17220 views
  • Discussion

    how to convert text string to integer in VerilogA?

    Category: Mixed-Signal Design

    By DavidLou

    •

    updated over 8 years ago by DavidLou

    12 replies • 27791 views
  • Discussion

    possible to instantiate Verilog module in VerilogA?

    Category: Mixed-Signal Design

    By DavidLou

    •

    updated over 8 years ago by DavidLou

    6 replies • 22148 views
  • Discussion

    Generating a spectre netlist(.scs) with a corner conditions in command line

    Category: Mixed-Signal Design

    By rotanudad

    •

    updated over 8 years ago by Andrew Beckett

    1 replies • 15808 views
  • Discussion

    Waveform Viewer selection in AMS Designer

    Category: Mixed-Signal Design

    By DavidLou

    •

    updated over 8 years ago by DavidLou

    10 replies • 24465 views
  • Discussion

    userdata file in Liberate

    Category: Mixed-Signal Design

    By anandmohan

    •

    updated over 8 years ago by anandmohan

    1 replies • 15279 views
  • Discussion

    Doubt reg a .lib file parameter

    Category: Mixed-Signal Design

    By anandmohan

    •

    updated over 8 years ago by Guangjun Cao

    3 replies • 16934 views
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