• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. PCB Design & IC Packaging (Allegro X)

PCB Design & IC Packaging (Allegro X)

CDNS Forum PCB Categories

Allegro X PCB Editor

Allegro X Capture CIS

Allegro X System Capture (EE Cockpit)

Allegro X Pulse & EDM

Allegro X APD

Allegro X Scripting - Skill

Allegro X Scripting - TCL

PCB Design Archive

Design Entry HDL

PSpice

Licensing & Installation

  • Leaderboard

    PCB Design

    • 1
      CF202606104231
      CF202606104231 45 Points
    • 2
      avant
      avant 25 Points
    • 3
      SG20260713408
      SG20260713408 20 Points
    • 4
      TL202608111936
      TL202608111936 15 Points
    • 4
      Electro Node
      Electro Node 15 Points
  • Leaderboard

    PCB Design

    • 1
      steve
      steve 15,523 Points
    • 2
      oldmouldy
      oldmouldy 10,615 Points
    • 3
      eDave
      eDave 7,286 Points
    • 4
      DavidJHutchins
      DavidJHutchins 5,231 Points
    • 5
      redwire
      redwire 4,178 Points

Feedback, Suggestions, and Questions

Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Forum - Thread List

Latest Posts

  • Discussion

    edit signal names in HDL following a group copy

    Category: PCB Design

    By K2J4

    •

    updated over 15 years ago by Mike Veal

    4 replies • 17436 views
  • Discussion

    Batch edit multiple package symbols

    Category: PCB Design

    By nimoster

    •

    updated over 15 years ago by nimoster

    2 replies • 14848 views
  • Discussion

    get drc's on pin delays when i change my cross-section brd thickness

    Category: PCB Design

    By jdkelly

    •

    updated over 15 years ago by redwire

    1 replies • 850 views
  • Discussion

    how to import the netlist into allegro created by orcad capture??

    Category: PCB Design

    By Prince Moses

    •

    updated over 15 years ago by Prince Moses

    2 replies • 20717 views
  • Discussion

    How to pick component center point

    Category: PCB Design

    By Cad Engineer

    •

    updated over 15 years ago by redwire

    1 replies • 15797 views
  • Discussion

    UPDATING SYMBOL PADSTACK

    Category: PCB Design

    By girish

    •

    updated over 15 years ago by hpattie

    1 replies • 14273 views
  • Discussion

    Need Help with Allegro PCB editor 16.2

    Category: PCB Design

    By HGarcia

    •

    updated over 15 years ago by anniesmom1999

    8 replies • 18236 views
  • Discussion

    My cadence orcad does't creat a netlist versions 16.3

    Category: PCB Design

    By awawa

    •

    updated over 15 years ago by awawa

    1 replies • 745 views
  • Discussion

    Swapping module pins.

    Category: PCB Design

    By EA PCB Design

    •

    started over 15 years ago

    0 replies • 13580 views
  • Discussion

    Pin order after swapping pins.

    Category: PCB Design

    By EA PCB Design

    •

    started over 15 years ago

    0 replies • 14364 views
<>

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2026 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information