• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. PCB Design & IC Packaging (Allegro X)

PCB Design & IC Packaging (Allegro X)

CDNS Forum PCB Categories

Allegro X PCB Editor

Allegro X Capture CIS

Allegro X System Capture (EE Cockpit)

Allegro X Pulse & EDM

Allegro X APD

Allegro X Scripting - Skill

Allegro X Scripting - TCL

PCB Design Archive

Design Entry HDL

PSpice

Licensing & Installation

  • Leaderboard

    PCB Design

    • 1
      avant
      avant 55 Points
    • 1
      KS202606109251
      KS202606109251 55 Points
    • 3
      BC202603263145
      BC202603263145 26 Points
    • 4
      JV202605125312
      JV202605125312 20 Points
    • 4
      JR202606119023
      JR202606119023 20 Points
  • Leaderboard

    PCB Design

    • 1
      steve
      steve 15,598 Points
    • 2
      oldmouldy
      oldmouldy 10,805 Points
    • 3
      eDave
      eDave 7,391 Points
    • 4
      DavidJHutchins
      DavidJHutchins 5,231 Points
    • 5
      redwire
      redwire 4,458 Points

Feedback, Suggestions, and Questions

Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Forum - Thread List

Latest Posts

  • Discussion

    How to associate symbols / footprints in standard libraries

    Category: PCB Design

    By glias

    •

    updated over 16 years ago by glias

    9 replies • 19945 views
  • Discussion

    Question on dynamic pours

    Category: PCB Design

    By kanonfodder

    •

    updated over 16 years ago by Nagaraj Shanmu

    2 replies • 13831 views
  • Discussion

    Cannot update NET_SPACING_TYPE

    Category: PCB Design

    By kulabong

    •

    started over 16 years ago

    0 replies • 13467 views
  • Discussion

    one design spanning multiple boards

    Category: PCB Design

    By mpfleger

    •

    updated over 16 years ago by mpfleger

    3 replies • 15931 views
  • Discussion

    How to get a pour to update the connections?

    Category: PCB Design

    By kanonfodder

    •

    updated over 16 years ago by kanonfodder

    2 replies • 13993 views
  • Discussion

    Move symbol/component to other layer

    Category: PCB Design

    By brthlsn

    •

    updated over 16 years ago by Ejlersen

    6 replies • 10715 views
  • Discussion

    Is there a diff between 9.2 & 16.3 EDIF or MIN formats?

    Category: PCB Design

    By Matty

    •

    updated over 16 years ago by Matty

    8 replies • 4454 views
  • Discussion

    Printing to PDF from Allegro Design Entry CIS

    Category: PCB Design

    By Goblin59

    •

    updated over 16 years ago by Ejlersen

    5 replies • 17148 views
  • Discussion

    Request sucess story of Cadence SiP SI or good case.

    Category: Allegro X APD

    By Luke Park

    •

    updated over 16 years ago by TeamAllegro

    1 replies • 14386 views
  • Discussion

    Moderator - help!

    Category: PCB Design

    By hpattie

    •

    updated over 16 years ago by archive

    3 replies • 861 views
<>

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2026 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information