Cadence Community

Forum - Thread List

Discussion

adexl remove test Locked

4617 views

2 replies

Latest over 1 year ago
by dogman4
Answered

how to auto void the dynamic copper to via pad less hole with same net 0

2559 views

3 replies

Latest over 1 year ago
by avant
Suggested Answer

Get net name error in Hierarchy design 0

2127 views

1 reply

Latest over 1 year ago
by CadAP
Not Answered

TCL problem when get net name of pin in hierarchy design 0

2176 views

1 reply

Latest over 1 year ago
by CadAP
Answered

Trace loop in OrCad X 0

2214 views

3 replies

Latest over 1 year ago
by mahimag
Discussion

Figures missing in the RF Design Blogs article of "Measuring Fmax for MOS Transistors" Locked

3451 views

2 replies

Latest over 1 year ago
by Andrew Beckett
Suggested Answer

AllegroX SPACING rule precedence 0

4686 views

1 reply

Latest over 1 year ago
by techiecs
Discussion

Display Resource Editor: Different Colors for Schematic and Layout Axis Locked

6108 views

3 replies

Latest over 1 year ago
by sgcad
Discussion

How do you create a footprint symbol for a DIE that will be referenced in system capture schematic?

15289 views

1 reply

Latest over 1 year ago
by kanecharle
Discussion

Flattening techLib VIA0/VIA1 Locked

706 views

0 replies

Started over 1 year ago
by Mallappa T
Answered

Test point creation workflow recommendations? 0

8078 views

5 replies

Latest over 1 year ago
by JS202408156358
Not Answered

Find all the lock components in the schematic and unlock them 0

2893 views

2 replies

Latest over 1 year ago
by DW20241101210
Discussion

Quantus not running an returning error with no description Locked

6176 views

1 reply

Latest over 1 year ago
by ConradJ
Discussion

How to get maximum value of s11 Trace Locked

4767 views

2 replies

Latest over 1 year ago
by NS202408066722
Discussion

How to edit a footprint in an existing design in OrCAD X Presto

2960 views

2 replies

Latest over 1 year ago
by mahimag