• Discussion

  Error coming up creating PCB Editor SPMHDB-195 "text line is outside of the extents" Locked

  4438 views
  2 replies
  Latest over 14 years ago
  by stellar
• Discussion

  how to add the library to cadence allegro? How to update it? Locked

  14643 views
  1 reply
  Latest over 14 years ago
  by KoolKat
• Discussion

  Parasitic annotation and simulation using the sbaLib devices Locked

  13515 views
  0 replies
  Started over 14 years ago
  by KMan2011
• Discussion

  Uniform congestion among metal layer Locked

  13342 views
  0 replies
  Started over 14 years ago
  by Teru
• Discussion

  How to select a single segment of voids?

  13705 views
  3 replies
  Latest over 14 years ago
  by stillfish
• Discussion

  IC 6.1.3 Licence ChekOut and CheckIn Locked

  15204 views
  3 replies
  Latest over 14 years ago
  by Andrew Beckett
• Discussion

  Sockets / FPGA's Locked

  942 views
  1 reply
  Latest over 14 years ago
  by redwire
• Discussion

  how to Enable/disable covergroups with in classes Locked

  2338 views
  0 replies
  Started over 14 years ago
  by SACHPAT
• Discussion

  ODB++ Inside Locked

  13578 views
  0 replies
  Started over 14 years ago
  by eDave
• Discussion

  lvsIgnore, netlistIgnore Locked

  16478 views
  1 reply
  Latest over 14 years ago
  by skillUser
• Discussion

  Gate Level Simulation Locked

  13587 views
  0 replies
  Started over 14 years ago
  by Mandate
• Discussion

  How to create voids on existing shapes?

  14104 views
  2 replies
  Latest over 14 years ago
  by wildSheep
• Discussion

  How to get Trace angle value?

  13602 views
  1 reply
  Latest over 14 years ago
  by Silver John
• Discussion

  Netlisting parasitics as sub-circuit Locked

  13799 views
  1 reply
  Latest over 14 years ago
  by Andrew Beckett
• Discussion

  Cadence Setup issue Locked

  13632 views
  1 reply
  Latest over 14 years ago
  by Andrew Beckett